Lab 08 - ECE 421L 

Authored by Jeevake Attapattu and Henry Chan

attapatt@unlv.nevada.edu, chanh6@unlv.nevada.edu

1 December 2014

Generating a test chip layout for submission to MOSIS for fabrication

For this lab we formed into groups to put test structures on a chip.

Each test circuit has its own power but ground is shared between the circuits.

Power is not shared between the circuits so that a vdd! to gnd! short in one circuit does not make other circuits inoperable.

The first action is creating a backup. Type tar -cvf "date"CMOSedu.tar CMOSedu/. This will create a tar file with all the project and homework saved. In place of "date" type in the date creating the backup. Unce the backup has been created type gzip "date"CMOSedu.tar.tar. This will create a .tar.gz file witch is significantly smaller.

Use MobaXTerm to download the file to your own pc then upload to a backup site such as dropbox or google drive.

Launch Virtuoso.

You will be using previous work from tutorial 5 & 6.

Make sure that you update intances when copying.
Open a new layout called pad since we are going to create a pad. Start with the pad layer. The pad layer is going to be used later for alignment purposes. According to the tutorial we need to use a 120umx120um pad.

 
Use a 75umx75um metal 3 layer and an overglass layer of 63umx63um. Notice that 75-63=12. That is 6um on each side which is specified by the MOSIS design rules.

 
The last component is to add a pin on metal 3. Make sure that it is inputoutput and name it pad. Select the text and change the height. I chose 16.

 
Next create a new layout called pad frame. Type i and place an instance of the pad you just created. Place another metal 3 inputoutput pin on top. Call it pin<1>. This notation is to indicate an array. Use c to copy and select 12 rows and 12 columns. Delete the cells in the center and corners.  You should have something similar to the image below.

 
Now we need to number each pin individualy. Remove the pad layer on the pad layout. This will help speed up selection. Follow the numbering scheme in the tutorial. You should have something similar to the layout below.

 
Now create symbol and schematic for the pad. For the schematic simply place an inputoutput pin called pad. Create the symbol and simplyfy as below.

 
Now do the same for the pad frame. As always DRC and LVS.

 
I later added metal1, metal2, via, and via2 so that my pads can connect with any metal layer.
The rest of the tutorial involves adding additional items and connecting them to the frame.  We are going to skip that part becuase we will not be using that information in lab 8.
 
Our chip includes the following test structures:

• 30u/0.6u NMOS (3 pins, DN, GN, SN, connect the p+ body, B, of the NMOS to the chip's ground pin)
• 30u/0.6u PMOS (4 pins, DP, GP, SP, and BP)
• Inverter made using 30u/0.6u NMOS and 60u/0.6u PMOS (3 pins, in, out, VDD_inv)
• 61 stage ring oscillator using 6u/0.6u MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
• 20k n-well resistor (2 pins)
• 20k hi-res poly resistor (2 pins) 
• 1k n+ resistor (2 pins)
• 1k p+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)
• Bandgap reference (2 pins, VDD_bg and Vref)

 The Layout
 
It DRCs and LVSs!

Test Structures:

30u/0.6u NMOS (3 pins, DN, GN, SN, with the body, B, connected to the chip's ground pin)

• The Drain (DN) is connected to pin 1
• The Gate (GN) is connected to pin 2
• The Source (SN) is connected to pin 3

30u/0.6u PMOS (4 pins, DP, GP, SP, and BP)

• The Drain (DP) is connected to pin 4
• The Gate (GP) is connected to pin 5
• The Source (SP) is connected to pin 6
• The Body (BP) is connected to pin 7

Inverter made using 30u/0.6u NMOS and 60u/0.6u PMOS (3 pins, in, out, VDD_inv)

• VDD_Inv is connected to pin 14
• In is connected to pin 15
• Out is connected to pin 16
• GND is connected to pin 20 (gnd!)

61 stage ring oscillator using 6u/0.6u MOSFETs with off-chip buffer (2 pins, VDD_osc and Ocs_out. Ground connected to pin 20)
Click on the image for a closer view.

• VDD_osc is connected to pin 18
• osc_out is connected to pin 17
• GND is connected to pin 20 (gnd!)

• One terminal is connected to pin 8
• The other terminal is connected to pin 13

The sheet resistance is approximately 1k. This requires 20 squares. We have used 36um x 1.8um.

• One terminal is connected to pin 8
• The other terminal is connected to 12
  

1k n+ resistor (2 pins)

• One terminal is connected to pin 8
• The other terminal is connected to 11

1k p+ resistor (3 pins, need n-well to isolate the p+ from the p-substrate and the n-well needs to be tied to a voltage >= either side of the resistor)

• One terminal is connected to pin 8
• The other terminal is connected to pin 9
• A third connection needs to be made to ensure the n-well does not source current from the resistor.
• This third connection is tied to pin 10 and needs to be tied to a voltage that is greater than the voltage at either side of the resistor during testing.
  

reference (2 pins, VDD_bg and Vref)

• VDD is connected to pin 19
• Vref (1.25V) is connected to pin 21
• GND is connected to pin 20 (gnd!)
  

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