Homework assignments and Project Information for EE 420 Engineering Electronics II and ECG 620 Analog IC Design, Spring 2014

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.

HW#20 – A24.9, due Wednesday, May 7

HW#19 – A24.5, due Wednesday, April 23

HW#18 – A24.6, due Monday, April 21

HW#17 – A24.4, due Wednesday, April 16

HW#16 – A24.2 and A24.3, due Monday, April 14

HW#15 – A23.10 and A24.1, due Monday, April 7

HW#14 – A23.3, A23.5, and A23.7, due Wednesday, April 2

HW#13 – A22.13 and A23.1–A23.2, due Monday, March 31

HW#12 – A22.4 and A22.7, due Wednesday, March 26

HW#11 – A22.1, due Monday, March 24

HW#10 – A21.14, A21.15, and A21.22, due, Wednesday, March 5

HW#9 – A21.10, A21.11, and A21.19, due, Monday, March 3

HW#8 – A21.1, A21.3, A21.4, and A21.18, due Wednesday, February 26

HW#7 – A20.26, A20.28, and A20.29, due Monday, February 24

HW#6 – A20.11, A20.12, A20.14, A20.17, A20.21, and A20.22, due Wednesday, February 19

HW#5 – A20.2, A20.4, A20.6, and A20.8, due Wednesday, February 12

HW#4 – A9.29, A9.30, and A20.1, due Monday, February 10

HW#3 – A9.5, A9.9, A9.12, and A9.15, due Wednesday, February 5

HW#2 – A9.3, A9.4, A9.10, and A9.13, due Monday, February 3

HW#1 – A9.1 and A9.2, due Monday, January 27

Course project – using On's C5 process (process information can be found at CMOSedu.com, MOSIS.com, or at On's website, minimum L is 600 nm, SPICE models are found in C5_models.txt) design an op–amp that can operate with a VDD between 2 and 5 V while driving a 10 pF (max) and 1k (min) load. 

Other requirements are:

• DC open–loop gain > 60 dB under all load and VDD conditions
• Gain–bandwidth product should be > 100 MHz
• Slew–rate with maximum load > 100V/microsecond

Your report should contain, at least, the following:

• Simulations showing large– and small–signal operation, along with limitations, using +1 gain non–inverting and –1 gain inverting op–amp topologies
• Show operation, including settling time and slewing, with no load and varying loads
• Your detailed design considerations
• Show schematics with a comparison between hand calculations and simulations along with comments 
• A table summarizing results such as input CMR as a function of VDD, unity–gain frequency, power, slew–rate, CMRR, PSRR, output swing as a function of VDD, etc.

This is not a team effort. A significant portion of your grade will be based on your report. I will grade these reports with you present. You will need to come to my office where we’ll go through your design, simulations, and report. Your report is due at the beginning of class on Wednesday, April 30, though you can bring your SPICE files with you when we meet.

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