Final Project - EE 420L - Design of a Band-Gap Reference (BGR)                                                             using the CD4007 CMOS Transistor Array

Jonathan K DeBoy
deboyj@unlv.nevada.edu
24 April 2015

Introduction

Using as many diodes, resistors, and capacitors as needed, along with two CD4007 chips from the same production lot (see date code on the top of chip) to ensure current mirrors are possible, design and build a bandgap voltage reference (BGR). Your report, in html, should detail your design considerations, simulation results (using the models you generated in lab 8), and measured results showing the BGR's performance (how the reference voltage changes with VDD). It would be good, but it's not required, if you could also characterize the BGR performance with temperature.

The Band Gap Reference

Below is a hand derivation of the reference voltage and how it varies with temperature. We picked 4 diodes as our k value and determined all other values from there. The BMR structure with a PMOS current mirror rejects (slightly) changing in the power supply voltage.

Schematic. 3 CD4007 chips were used to generate this circuit. Actual diodes were used instead of pnps transistors.

Below are the simulated results sweeping VDD from 0 to 20V (twice of what we simulated in real ife). Multiple plots are for different temperatures (degrees C):
Red: 0     Blue: 50     Green: 100     LightBlue: 150     Purple: 200




Above is our temperature coefficient (in parts per million ppm) as it varies in temperature applied. It is about 0.0008ppm


Our actual results measuring Vref while sweeping VDD from 1 to 10V are below:
VDD (V) Vbiasp (V) Vref (V)
0.998 0.03 -0.0226
1.998 0.556 0.645
2.997 1.538 0.859
3.996 2.526 1.058
4.996 3.516 1.261
5.996 4.508 1.475
6.995 5.5 1.701
7.994 6.493 1.943
8.993 7.486 2.203
9.993 8.48 2.479

Graphical Representaiton:




Conclusion


To increase the performance of our Band-Gap Reference (BGR) in terms of power supply rejection, we could place a differential amplifier at the drains of both of the PMOS in the current mirror for better matching. We decided against using an additional 2 chips to create the diff-amp. We have to use the simulation's results to determine the temperature performance of our BGR since testing that parameter in real life requires us to make sure all the components of the circuite raise at the same time.

LTspice model:

*
* Long channel models
* Level=1 models VDD=5V
*
.MODEL N_level1 NMOS LEVEL = 1
+ TOX    = 1.13E-9
+ VTO    = 0.8
+ GAMMA  = 1
+ KP     = 5.38E-6
+ LAMBDA = 0.05
*
.MODEL P_level1 PMOS LEVEL = 1
+ TOX    = 1.13E-9
+ VTO    = -1
+ GAMMA  = 1
+ KP     = 4.8E-6       
+ LAMBDA = 0.05
*


 
 
 
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