Final Project - EE 420L 

Authored by: Roman Gabriele Ocampo
Email: ocampor5@unlv.nevada.edu
Date: May 5, 2014
  

Design Of A General Purpose Op-Amp

Prelab:
Lab Description and Goals:

The Op-Amp:
In the process of creating this op-amp, the first major design constraint was the limitation of only two CD4007 chips. If one looks at the CD4007 datasheet, each chip has 3 pairs of NMOS and PMOS transistors. Each N/P pair is gate connected, which means that while each chip has 6 transistors (12 total), only 3 per chip (6 total) can be used if independent gates are desired.
 
As such, sacrifices must be made. In class, a simple op-amp is created using a differential pair (with a current mirror load and tail) as the first stage with a push-pull amplifier as the second stage. Such a configuration would require at least 8 independet NMOS and PMOS gates (though the push-pull stage and the biasing current mirror can take advantage of the NMOS/PMOS tied gates and/or the tied drain/sources). Since only 6 independent gates are available, resistors must be used in place of the transistors in both the diff pair and the output stage. The final design is shown below. The pin associated with each transistor is included. The letter "a" denotes the upper CD4007 chip, while the letter "b" denotes the lower CD4007 chip.

The gain is significantly decreased in this design (as shown later). In this design, M6, M8, and M10 come from one chip (to ensure good matching for the M8/M10 current mirror) and M7 and M11 come from the other chip.

 
Open-Loop Gain:


The open loop gain of this design is only 25dB, which is roughly 17V/V. This is terrible. Ideally, the open loop gain of an op-amp would be infinity. The simple op-amp discussed in the book has a gain of 1,000V/V. The op-amp's low gain will result in significant errors when put into different closed loop gain configurations (shown below).
 
Noninverting Topologies:

The closed loop gain in the noninverting topology is ideally Av=1+R2/R1.
 
For Av=1:


From the simulation, the gain is 0.86V/V. From the experiment, the gain is 158m/194m = 0.81V/V.
 
For Av=5:


From the simulation, the gain is 3.55V/V. From the experiment, the gain is 624m/192m = 3.25V/V
 
For Av=10:


From the simulation, the gain is 5.84V/V. From the experiment, the gain is 968m/184m = 5.26V/V.
 
Inverting Topologies:

The closed loop gain of the noninverting topology is Av=-R2/R1
 
For Av=-1:


From the simulation, the gain is -0.66V/V. From the experiment, the gain is -110m/182m = 0.60V/V.
 
For Av=-5:


From the simulation, the gain is -3.15V/V. From the experiment, the gain is -544m/188m = -2.89V/V.
 
For Av=-10:


From the simulation, the gain is -5.30V/V. From the experiment, the gain is -876m/188m = -4.66V/V.
 
Conclusion:
From the simulations and experimental results above, we can conclude that the op-amp I designed does indeed exhibit operational amplifier behavior, albeit having an extremely low open loop gain. In the different closed loop gain configurations, the output does achieve different gains for different configurations, but it is nowhere near the ideal values due to its low open loop gain.
 
To improve this design, more chips should be made available. Rather than having resistors on the diff pair, improvements can be made by substituting a PMOS current mirror load. For the output stage, a proper push-pull amplifier can be included. Including these changes would significantly increase the open-loop gain of the op-amp, reducing the closed loop gain errors.
 
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