Homework assignments and Project Information for ECG 722 Mixed-Signal Circuit Design, Fall 2016

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.
• Homework is due by 5 PM pacific time on the due date  
  

HW#18 – A7.6 and A7.7, due Monday, Nov. 28
HW#17 – A7.5, due Wednesday, Nov. 16
HW#16 – A7.3 and A7.4, due Wednesday, Nov. 9  
HW#15 – Questions 7.1–7.5 on page 282 (and verify the solutions at CMOSedu are correct), due Wednesday, November 2
HW#14 – Questions 6.7 and 6.8 on page 232 (and verify the solutions at CMOSedu are correct), due Monday, October 31
HW#13 – Question 6.3 on page 231 (and verify the solution at CMOSedu are correct), due Wednesday, October 26
HW#12 – A6.4 and A6.5, due Monday, October 24
HW#11 – A5.10–A5.11, due Monday, October 17
HW#10 – A5.7–A5.9, due Wednesday, October 12
HW#9 – A5.1–A5.4, due Monday, October 10
HW#8 – A4.5–A4.8, due Wednesday, October 5    
HW#7 – A4.1–A4.4, due Monday, October 3
HW#6 – A2.8 and A2.11, due Wednesday, September 28 
HW#5 – A1.11, A1.12, and A2.5, due Monday, September 26
HW#4 – A2.3 and A2.4, due Wednesday, September 21
HW#3 – A1.9–A1.10 and A2.1–A2.2, due Wednesday, September 14
HW#2 – A1.5, A1.7, and A1.8, due Wednesday, September 7
HW#1 – A1.1–A1.3, due Wednesday, August 31  

ECG 722 Course Projects – Design a replacement for the ADC seen in Fig. 9.32 using a continuous–time topology (no switched–capacitors and no non–overlapping clock signals). In other words replace the switched–capacitors with resistors. Your project report should detail:

• The reasons for the topology you selected including design considerations
• Design of a ring oscillator to generate 8, equally–spaced, edges for use in your topology 
• It will be useful if you can adjust the frequency of your oscillator design so you can run the ADC with slower clocks to look at how the performance changes with clock frequency (e.g., your oscillator is voltage–controlled)  
• Design of a comparator. You can copy the one I placed in the Ch9_MSD_LTspice folder but a different design may improve performance
• Design of an amplifier for use in the integrator. Again, you can copy the one I placed in the Ch9_MSD_LTspice folder but a different design may improve performance. 
• Feedback signal control and logic. Circuitry to control the width and, perhaps amplitude, of your feedback signal.  

• Hand calculations with comparisons to simulations (see if you can run slow to make theory match simulations)  

• Power consumption of your design compared to the design in Fig. 9.32
• SNR, BW, and Neff comparison between your design and the one seen in Fig. 9.32 (use the MATLAB scripts in Ch9_MSD_LTspice)  
• Characterization of the DC behavior of your design, are there dead zones? 

• Investigation of a first–order topology's performance compared to a second–order topology. Can you run the second–order topology slower, use only 4 paths, and beat a first–order's performance that uses 8 paths? You may decide that you want to go with a second–order topology for your design. Note that this comment should serve as an example of me making an arbitrary suggestion with the hope that you think of a better way to design the converter. 

• Email me your (ensure, if you send raw simulation files, that the size is < 20 MB) zipped–up design directory and project report in PDF or Word formats.
• I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) 
• I should receive the electronic report and zipped–up simulation directory of your design via email (r.jacob.baker@unlv.edu) before 4 pm on Monday December 5, 2016.
• I will meet with you one–on–one to grade the project sometime during the week of Dec. 1  
• Grading will be heavily biased towards you documenting attempts to think beyond what I've given you here, in Ch9_MSD_LTspice, and in the book. If you simply answer all of the questions listed here in your report and I see no further attempts at creative thought you won't get a good grade (please make sure you understand this else you will be disappointed with your grade).

Note that if you haven't taken courses in circuit design, like EE 420/ECG 620 and EE 421/ECG621, then you can use the transistor–level designs without modifications found in Ch9_MSD_LTspice. If you have taken these courses, or you have the knowledge from some other activity, like your job, then feel free to design your own circuits. 

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