ECG 720

Homework assignments and Project Information for ECG 720 Advanced Analog IC Design, Fall 2019

Homework guidelines are found here.
Note that an A in front of the problem indicates an additional problem from here.
Submit homework, in PDF, to the course TA, via email by 5 PM on the day the homework is due.

No late homework accepted.
Do not cc the instructor when you email your homework to the course TA.
The course TA will cc the instructor when he emails your graded homework back to you

HW#12 – A30.3–A30.5, due Wednesday, November 27
HW#11 – A29.1, A29.2, A29.5, A29.8, and A29.10, due Wednesday, November 20
HW#10 – A28.1, A28.2, and A28.7, due Wednesday, November 13
HW#9 – A31.6 and A31.7, due Monday, Wednesday, November 6
HW#8 – A31.1–A31.5, due Wednesday, October 30
HW#7 – A25.1–A25.3, and A25.5, due Wednesday, October 16
HW#6 – Check the online solutions for end–of–chapter problems for Ch. 26. Generate a better, and more correct, solution for any of the online solutions that aren't high–quality. Feel free to put your name on your solution. It will replace the existing solution if it's better, that is, clear and concise, due Wednesday, October 9
HW#5 – A26.1–A26.4, due Wednesday, October 2
HW#4 – Explain, in your own words, Correlated Double Sampling (CDS) and give an example of the use of CDS using LTspice (hint: use the flicker noise sims in the extras folder along with two switches, two capacitors, and a VCVS to show a change in the output noise spectrum), book problem 8.6 and verify your answer using LTspice, explain what happens to the output SNR when you integrate the output of the circuit seen in Fig. 8.29 (again, verify your answer using LTspice), A8.5, and A8.13, due Monday, September 30

HW#3 – A8.1–A8.3, due Wednesday, September 18

HW#2 – A3.5, A3.8–A3.10 (from Ch3_MSD_hw.docx), due Wednesday, September 11

HW#1 – A3.1–A.3.4 (from Ch3_MSD_hw.docx), due Wednesday, September 4

Course project – using On's C5 process (process information can be found at On's website, minimum L is 600 nm, SPICE models are found in C5_models.txt) design an analog front–end for converting current from an APD into an output voltage. Assume the APD has the structure seen here. The APD's cathode (n–well) will be connected to a 15 V DC supply (or whatever is needed for your design). The APD's anode (p+ in the n–well) will be connected to ground through a resistor. Determine, based upon the information you have, the value of the resistor and how it influences the biasing and noise performance (SNR). Assume the APD's depletion capacitance is negligible. Do you have to AC couple the APD's current into the analog front end or can the diode's bias current be DC connected to the front–end's input?

Your report should detail the design and evaluation of the following:

Total gain: First Stage – 30kΩ (Transimpedance amplifier, TIA) and Second Stage 10–20x V/V
Study of the need for inclusion of a 2nd stage
TIA Bandwidth minimum of 250 MHz
Input referred noise: < 5 pA/√Hz but preferrably 1.5 pA/√Hz
1.5 – 2 V output swing
3.3 or 5 V power supply operation with less than 5 mA current consumption
Amplifier output signal is designed to drive high impedance loads (use 1 pF)
Slew–rate with maximum load > 100V/microsecond = 100 mV/nanosecond

Your report should contain, at least, the following:

Simulations showing large– and small–signal operation
Show operation, including settling time and slewing, with no load and varying loads
Noise performance including the significance of capacitance on the input of the front–end (which would occur using an off–chip APD)
Your detailed, but concise, design considerations
Discussions on using the front–end with the C5 APDs (this needs to be practical and clear)
Show schematics with a comparison between hand calculations and simulations along with comments
A table summarizing results concisely

This is not a team effort. A PDF of your report and zipped-up simulation files are due (email to rjacobbaker@gmail.com) at 5 PM on Wednesday, November 27.

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