Homework assignments and Project Information for ECG 720 Advanced Analog IC Design, Fall 2013

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.

HW#19 – A30.1, due Wednesday, November 27

HW#18 – A29.8–A29.10, due Monday, November 25

HW#17 – A29.1–A29.3, A29.7, due Monday, November 18

HW#16 – A28.1–28.7, due Wednesday, November 13

HW#15 – A27.3, due Wednesday, November 6

HW#14 – A27.1, due Monday, November 4

HW#13 – A21.31, A22.11, and A22.12, due Wednesday, October 30

HW#12 – A9.21 and A20.31, due Monday, October 28

HW#11 – A8.15 and design a series–shunt fb amp in the 50 nm process that can drive 50 ohms (comment on the limitations of your design), due Wednesday, October 16

HW#10 – A8.6, A8.12, and A31.5, due Monday, October 14

HW#9 – A8.17 and A31.14, due Wednesday, October 9

HW#8 – re–work quiz 5 and verify your results with simulations and A31.13, due Monday, October 7

HW#7 – A8.16 and A31.11–A31.12, due Wednesday, October 2

HW#6 – A8.11, A8.13, and A31.10, due Monday, September 30

HW#5 – A8.10 and A31.8–A31.9, due Wednesday, September 18

HW#4 – A8.9 and A31.7, due Monday, September 16

HW#3 – A8.7–A8.8 and A31.6, due Wednesday, September 11

HW#2 – A8.3–A8.5 and 31.2–A31.4, due Monday, September 9

HW#1 – A8.1–A8.2 and A31.1 due Wednesday, September 4

Course projects – Using ON's C5 process, 500 nm CMOS, design a low–noise transimpedance amplifier (TIA) for use in a LADAR system. The simulation schematic for the system is seen below. The input to the TIA is an Avalanche PhotoDiode (APD) biased with a 40 V DC supply through a 100k resistor. The APD is modeled using a current source having rise– and fall–times of 1 ns and a pulse width of 3 ns (FWHM is 4 ns). Note the direction of the APD's current (it flows out of the input of the TIA only). The diode's capacitance is modeled using the 2.5 pF capacitor. The current from the APD is AC coupled through a 100 pF cpacitor to the TIA. The 1 pF and 10 nH components model the parasitics associated with packaging the TIA. The TIA should drive a 50–ohm load. 

• Your report should detail your design considerations, schematics, and simualtion results
• Of course your report should compare your hand calculations with simulation results for AOL, ACL, Beta, Rinf, and Rof
  
• Your design should have four connections (only): input, output, vdd, and gnd
• It's desirable to have large gain, say 100 kohms, and low input–referred noise, say 100 nA RMS
• However, gain will have to be traded off for speed
  
• Fully characterize the operation of your design: noise, transient respoinse, AC bandwidth, DC sweep
• Note that it's desirable to have clean settling response (no over– or under–shoot) in order to keep the system's resolution high
• Power supply voltage is 5 V and the output should be, under quiescent conditions, at, around, 500 mV so it can move towards 5 V with an input pulse
• If the gain is 50k then a 50 uA input pulse would result in the output pulsing from 500 mV to 3 V
• There is nothing special about 500 mV. You are the designer and you know the input and desirable output (so you design the TIA!)
  
• Comment on how the diode's capacitance influences the noise performance
• Does the APD's dark current influence the performance of the system?
• If the 50–ohm load is the input resistance of a data converter having a resolution of 1 mV then what is the minimum input current your design can resolve?
• The report and simulation files should be emailed to me (r.jacob.baker@unlv.edu) before 4:00 PM on Wednesday, December 4

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