Homework
assignments and Project Information for ECE 615 CMOS Mixed-Signal IC
Design,
Fall 2010
Homework
guidelines are found here.
Note that an A in
front of the problem
indicates an additional problem from
the book’s webpage,
not a problem from the
book’s end-of-chapter problems.
Project# 2 due
Wednesday, December 8 –
using the 50
nm process
from CMOSedu.com design, and simulate using LTspice, a continuous-time
K-Delta-1-Sigma modulator based upon the topology seen in Figure 6.24
of the
book but using an active integrator. Use the Matlab
scripts from CMOSedu.com to combine the paths together, for the digital
filtering, and to calculate the SNR. Assume the clock frequency is 250
MHz and
8 paths are used (for an equivalent clock frequency of 2 GHz).
HW#10 due Monday,
December 6, A7.1-A7.2
HW# 9 due Monday,
November 15, A6.1-A6.3
HW# 8 due Monday,
November 1, A5.3-A5.6
HW# 7 due Monday,
October 25, A5.1-A5.2
HW# 6 due Wednesday,
October 20 – A4.5-A4.9
Project# 1 due Monday,
October 18 – design
an anti-aliasing filter (AAF) using the 50 nm
process from
CMOSedu.com for use with a 10-bit ADC clocked at 100 MHz.
Use any topology you want to implement the filter. I would like, along
with a
PDF of your report, a zipped-up folder of simulations emailed to me
before
lecture on Oct. 13. Your grade will be based on the quality of your
report, the
performance of your filter, and your ability to identify the important
trade-offs. Stating the obvious, simulation results should be
integrated
together with your hand calculations and discussions. I will be looking
for
frequency response, time domain (to determine, for example, output
swing), and
distortion simulations. It would also be useful to simulate the
performance of
the AAF over temperature and with VDD variations and noise.
HW# 5 due Monday,
September 27 –
A3.1-A3.4
HW# 4 due
Monday, September 20 – A2.6-A2.10
HW# 3 due
Monday, September 13 – A2.3-A2.5
HW# 2 due
Wednesday, September 8 – A1.5-A1.8, A2.1-A2.2
HW# 1 due
Monday, August 30 – A1.1-A1.4