Chris Barr
Email: chrisbarr74@gmail.com
Linkedin: www.linkedin.com/in/barr-christopher
About Me:
I graduated from UNLV in
May, 2020 with a Bachelor of Science in Engineering; specialized in Computer
Engineering.
I chose this major because
I wanted to challenge myself and explore the subject of computer and
electronics.
On my free time I enjoy
playing basketball, going to the gym, playing video games with friends, and
exploring the city.
RED TEXT =
Off page link(s)
Projects
“Soccer_Blocker” Video Game – Junior Design
Digital Security Lock System –
Junior Design
MIPS Superscaler
Pipeline Processor
FM Transmitter
32x32 APD Camera System
CMOS Boost Switching Power Supply (SPS)
CMOS 4x Clock Multiplier
Lab Work
EE 421L: Integrated Circuit (IC) Design Lab
Lab 2: Design of a 10-Bit
Digital-to-Analog Converter (DAC)
Lab 3: Layout of a 10-Bit DAC
Lab 4: IV Characteristics and
Layouts of MOSFET’s using Cadence
Lab 5: Design and Layout of a
CMOS Inverter
Lab 6: Design and Layout of a CMOS
NAND Gate, XOR Gate, and Full-Adder
Lab 7: Design and Layout of an
Oscillator, 8-bit Gates, and a MUX/DEMUX
Lab 8: Layout of a Chip Frame
with former designs for submission to MOSIS for Fabrication
CPE 300L: Digital Systems Architecture and
Design
Midterm:
Four Operators (+, -, *, /) Calculator
EE 221L: Circuits
Final:
Battery Voltage Monitor
Research
Opal
Kelly ZEM5305-A2 FPGA Tutorial
Extra Work
Current Digital-to-Analog Converter (iDAC) 8-Bit Layout [TowerJazz]
Wire Bonding
By: Chris Barr, Jett
Guerrero, Christina Cheung
Report and
Source Code Available
Soccer Blocker is an idea that was developed and built
upon the desire to use C code language and the DE2 board’s switches and
pushbuttons as a controller to create an interactive game. The focus was to
create a game that was simple enough for anyone to play but still captured the
player’s focus throughout the game.
The DE2 Board is an FPGA that was used in the making of
this project. An image of that board is on the right.
The player's objective is
to move the goalie to the left, middle, or right of the soccer goal in order to
block as many soccer balls as possible from entering the goal. The more soccer
balls that the player can block, the higher their score will be.
The process of creating
Soccer Blocker was comparable to making thousands of pictures using a multitude
of ‘for’ loops. This was an attempt to create a constant flow of images, like a
flip book.
An image on the left is
showcasing the game being played by a player.
Details of how this game
works is within the report. The code is also available.
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By: Chris Barr, Jett
Guerrero
Report, User
Guide, and Source Code Available
This device functions as a
security lock that requires a password code to unlock a system. The locking
system has a digital lock display to indicate the current condition, locked or
unlocked. The password code is resettable if one decides to change it.
To
enter the password, the FPGA would take in 4 values from the switches indicated
on the left image as “Code IN”.
After the password code is
entered, the right most push button must be pressed to unlock the system.
If one wishes to change
the passcode, one must first enter the valid password then switch on the left
most switch to enter a new passcode. In this mode, digital lock turns yellow.
For the outside lock, the
actuator would be attached to the GPIO pins on the DE2 board. Below is an image
showing that connection.
When
the passcode is entered correctly, a 3.3V is sent to one of the two GPIO pins
to unlock the actuator.
Details of the project,
the code, and how to use this project is located above.
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MIPS Superscalar Pipeline
Processor
By: Chris Barr, Jett
Guerrero
Report, Source
Code, and Demo Available
The goal of this project was
to create a faster processor that will have a faster execution time than the
regular pipeline processor (as shown below). The original processor could only
manage a single instruction on one clock cycle.
If the processor could
handle two instructions on a single clock cycle, then there would be an
increase in execution time. This method is called superscaling.
The image on the left
shows the result of executing two instructions at the same time, as oppose to
singular.
The processor would
receive a hardcoded text file of MIPS instructions, fetch the first two lines
of instructions, and it would proceed through a pipeline.
The new and improved MIPS pipeline processor is shown
down below:
This project was simulated
through ModelSim. Waveforms were used to view the
results.
The original pipeline
shows an execution time of 240ps:
The superscalar pipeline
shows an execution time of 170ps, that’s 1.41x faster:
For more details on this project, look at the report,
source code, or demo above.
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