Lab 4 - ECE 421L
IV characteristics and layout of NMOS and PMOS devices in ON's C5 process
Prelab Content
Prior to this lab session, we were tasked with backing up our previous work (as usual) as well as finishing Tutorial 2, in which we learned how to create the schematic and layout for an NMOS/PMOS transistor. We were also asked to perform a preliminary reading of the lab and were provided with some necessary information regarding the bodies of NMOS and PMOS devices in our upcoming simulations.
Postlab Report
The first task was to generate 4 schematics and simulations as follows:
A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.
I then downloaded the provided example cells (lab4.zip) for reference. The next task was to:
Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small).
Lastly, I similarly connected all 4 MOSFET termals of the PMOS device to probe pads as per the following instructions:
Backup
My online backup of my completed files can be downloaded here.