Lab 3 - ECE 421L
Prelab Content
Prior to this lab session, we were tasked with backing up our previous work (as usual) as well as finishing Tutorial 1. The purpose of this tutorial was to complete the following 10k n-well resistor layout and extract it for use in the main lab content. When determing the length of this n-well, I took into account that sheet resistance is 800 Ohms/square and the width of the n-well in order to match the ntap width must be 4.5μm. For a 10k resistor, we look at the equation 10k = 800*(L/4.5μm) and calculate a value of 56.25μm for the length. To measure this length in Cadence Virtuoso, one can simply use the hotkey (k) or manually create a ruler through the tools tab. Alternatively, one can also select the n-well layer and press the hotkey (q) or manually open the change object properties menu.
Postlab Report
For this lab, we used the 10k n-well resistor to create a layout for the 10-bit DAC schematic that we created in the previous lab.
After creating this layout, I verified that it was DRC and LVS clean.
After verifying the validity of the layout, this lab was complete.