Lab 7
EE 421L
Lab Description
Pre-lab work
Here is the 31 ring-oscillator by using 31 inverters connected in series with a feedback loop.
Here is the simulation of the 31-ring oscillator.
The compact schemactic version of the 31-ring oscillator by using buses.
The symbol for the ring oscillator.
The layout version of the ring oscillator.
The LVS verification.
Results from the symbol version of the ring oscillator.
4-Bit Inverter:
In this lab we will have to create a 4-bit inverter. Instead of layout 4 inverters, we can press Q on the inverter and change the instance name to I0<3:0> to simulated 4 inverters in one symbol, then connect buses on each end.
Here is the compacted 4x inverter.
Here is the inverter symbol.
Here is the simulation schematic.
Here are the results of that simulation.
8-Bit-Gates
We will now need to create 8-bit versions of the logic gates decribed at the start of this lab.
NOR Transistor Level
NAND Transisitor Level
NOR | ||
NAND | ||
OR | ||
AND | ||
NOT |
Zip file to lab 7