Lab 7

EE 421L 

Authored by Jimmy Ruangnol, 

(ruangnol@unlv.nevada.edu)

November 1, 2021

  

Lab Description

 

The purpose of this lab is to work with arrays and buses combined with different components.

During this lab, students will create schematic versions of inverters, OR gates, NOR gates, AND gates, and NAND gates. There will also be 8-bit versions of them to be tested. Demux/mux will also be created with their 8-bit version. Lastly, we will need the layout and schematic of 8-bit adders/full adders.

Pre-lab work

 


Here is the 31 ring-oscillator by using 31 inverters connected in series with a feedback loop.

 

Here is the simulation of the 31-ring oscillator.

 

The compact schemactic version of the 31-ring oscillator by using buses.

  

The symbol for the ring oscillator.

 
The layout version of the ring oscillator.

  

The LVS verification.

  

Results from the symbol version of the ring oscillator.

4-Bit Inverter:

 

In this lab we will have to create a 4-bit inverter. Instead of layout 4 inverters, we can press Q on the inverter and change the instance name to I0<3:0> to simulated 4 inverters in one symbol, then connect buses on each end.

 

Here is the compacted 4x inverter.

 

Here is the inverter symbol.

 

Here is the simulation schematic.

 

Here are the results of that simulation.

 

8-Bit-Gates

We will now need to create 8-bit versions of the logic gates decribed at the start of this lab.

 

NOR Transistor Level

 

NAND Transisitor Level

NOR
NAND
OR
AND
NOT
 
Here is the simulation schematic of all gates.
 
Here is the simulation results of these gates.
 
MUX/DEMUX:

The MUX and DEMUX are gates that allow a a signla path to be selected. The select lines chooses which outputs the inputs connect to.
Below is the transistor level of the 2 to 1 MUX/DEMUX and its symbol.
 
Here is the test schematic view of this 2 to 1 DEMUX
 
Here are the results of the simulation.

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