Lab

Lab 6 - EE 421L

Authored by Jimmy Ruangnol,

(ruangnol@unlv.nevada.edu)

October 5, 2021

Lab Description

The purpose of this week's lab is to design NAND and XOR gates to be implemented into a Full-Adder. A full adder is a digital logic circuit that can add two bits with an additional carry in bit and produce two bits with the carryout bit.

Pre-lab work

Go through Cadence Tutorial 4 seen here.
Create a CMOS NAND Gate.

The NAND gate is made with 6um/600nm PMOS and NMOS devices. Below are the schematics and layouts.

Here is the LVS to verify that the layout and schematic matches. It is also DRC verified.

We will need to test the NAND gate for logic consistency. Here is the schematic to test the NAND gate by using transisent simulation.

Here are the results

NAND Truth Table

A	B	A NAND B
0	0	1
0	1	1
1	0	1
1	1	0

Lab

Inverter:

We will then build a 6um/600nm inverter. Below are the schematic and layouts.

Verification through transient simulation.

XOR Gate:

Next we will be designing a CMOS XOR gate to be used as a building block for the full adder. Below are the schematic and layout.

Here is the test circuit for the the XOR gate to test logic levels through transisent simulation.

XOR Truth Table

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

Full Adder

With all the pieces assembled we can start working on the full adder. Below are the schmatic and layout of the full adder.

LVS verified!!!

Here is the test circuit for the the full adder to test logic levels through transisent simulation.

Full Adder Truth Table

cin	B	A	cout	S
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

There were issues within the full adder. The output above is not logic levels. I made sure that were was a global vdd, but it would still output this result. At the moment there was not enough time to fix the issue, but will be revsisted soon after the solution is found.

Always back up your work!

Here are the files for this lab (lab 6 zip file).

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