Lab 5 - EE 421L 

Authored by Jimmy Ruangnol, 

(ruangnol@unlv.nevada.edu)

September 21, 2021

  

Pre-lab work

 

Lab description

    The purpose of this lab is to design CMOS inverters by using NMOS AND PMOS MOSFET's. For this lab, we must crated two inverters. The first inverter is a 12um wdith PMOS and a 6um width NMOS. The second inverter is a 48um wdith PMOS and a 24um width NMOS. All the lengths for the MOSFET's will be 600nm.

 The inverters are simulated for the ouput voltages driving the capacitive loads. We ill be simulating for each inverter driving  a 100fF, 1pF, 10pF, and 100pF loads. This will be done in Ultrasim and spectre simulator. 

  

Here is the schematic and layout of the 12um/6um inverter.

 

 
Make sure to check for DRC and LVS of the inverters (see below).
 


 
Here is the schematic and layout of the 12um/6um inverter. Notice that M is equal to 4 times bigger than the original inverter.
 
 
Make sure to check for DRC and LVS of the inverters (see below).
 


 
Make a symbol of both inverters.
 

 

 
When creating a simulation make sure to set a global VDD through the settings below. You can reach this by going to ADE Steup > Stimuli.
 


After setting the global soruces, you should get the result below.
 

Simulations:

 
The inverters are simulated while driving capacitive loads of 100fF, 1pF, 10pF, and 100pF. This will be done in Ultrasim and spectre simulator with the test schematic above. We will be using a variable capacitor and parametric analysis.
 


ADE 12um/6um Inverter:
 

 
Ultrasim 12um/6um Inverter:



 
ADE 48um/24um Inverter:

 
Ultrasim 48um/24um Inverter:

 
From the simulation results, we can see that 48um/24um inverter takes a shorter amount of time to reach 5V, compared to the 12um/6um inverter. The MOSFETs are wider and have a lower resistance do to the wider channel.

Always back up your work.



Click the Lab5.zip file for more info.



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