Lab 2 - EE 421L 

Authored by Jimmy Ruangnol, 

(ruangnol@unlv.nevada.edu)

  

Today's date is 08/31/2021

  

Lab Description

 

The purpose of this lab is to design a 10-bit digital to analog converter and record its function. We will also be designing a DAC using n-well resistors. The function of a DAC is converting a a digital binary number to an analog output signal.

 

Prelab

 

To start the prelab you must download a Cadence library from here.

  

To properly install the file, please the instructions of Tutorial 1.

 

Transfer the lab2.zip file into the CMOSedu folder and preform the -unzip filename.zip command in Mobaxterm.

 

Also ensure that the library is defined in your cds.lib file

  

 

Open up the lab2 Cadence library and it should look like this.

  

 

Open the cell view file of 'sim_Ideal_ADC_DAC'.

 

 

 

Run the simlulation by 'Launch > ADE'. A window should pop up. The next step is 'Session > Load State > Cellview'. Make sure to pick the spectre_state file in the cell view.

 


  

You are able to change the color and thickness of the waveform by right clicking the pin names or waveforms. 

  

 In the given circuit, the voltage Vin is converted into a digital interger stored in the Analog-to-Digital converter bus B[9:0] on the left. The digitial value is then pass through the right Digital-to-Analog converter, which will output a stair step waveform. When the analog value is being converted to a digital value, the data can only define the discrete values.

 

This conversion can only occur when the analog value reaches a certain threshold. The formula for this value is this ratio: (Vdd/2^b). (Vdd is the input voltage and b is the number of bits). 

(Vdd/2^b) = 5/(2^10) = 4.88mV will be our minimum value for Vin. 

 

Lab 2:

 

The purpose of this lab is to design a 10 bit Digital-to-Analog converter  based on the figure below.

 

We needed to create a 2R aand R voltage divider in Cadence, similar to the figure above. After creating the schematic you can create a symbol by Create > Cellview > From Cellview.

 

You are able to manipulate the design, but must keep the red nodes the same. 

 

Next, create a new schematic and press "i" to instantiate the 1_Bit_DAC symbol 10 times and connect them like the picture below. 

 

  

After creating the schematic you can create a symbol by Create > Cellview > From Cellview.

 

 

Finding Resistance of DAC:

 

To find the overall ouput reistance, we can combine resistors of the same values that are parallel from each other until we get one final resistor in the circuit. Preferably start at the bottom and continuously combine the resistors. In the picture below we can see the methodology of this process and its final product. 

 

 

Finding Time Delay in DAC with 10pf load:

 

The next step is to determine the time delay within the DAC by using a 10pf capacitor load. All the bits besides B9 will be connected to ground. B9 will be connected to a pulse source. Since the input source is 5V then the output should be around 2.5V. 

 

To find the delay, use the equation: 

delay = 0.7RC >>> 0.7(10k)(10p) = 70ns should be our delay.

 

 In the simulation below we can see that the results match the calculations.  

  

Verifying the DAC Design:

 

In order to verify that the DAC design above is working correctly, the Ideal 10-Bit DAC will have to be swapped with the newly created one. We will run simulations to verify design is working.

 

Before simulations, it is absolutely imperative to change the simulation design paramters to the picture below to FORCE and convergence. Previous simulations will stop the output to fully form to the stop time. 

 

Run the simlulation by 'Launch > ADE'. A window should pop up. The next step is 'Session > Load State > Cellview'. Make sure to pick the spectre_state file in the cell view.

 

 

DAC under 10K Resistor Load:

  

 

With the DAC under the 10K resistor load, we can see that the output is a voltage divider. The input of 5V and the output being 2.5V.

 

DAC under 10pF Capacitor Load:

 

 

 

With the 10pf capacitor load added to the converter. We can see that the output is much smoother and added a delay.

 DAC under 10pF Capacitor and 10K Resistor Load:

 

For the final test. I added both the 10pF capacitor and 10K resistor to the load. The results show that the Vout is delayed due to the capacitor and the amplitude reduced significantly from the resistor.

In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). 


If the switches' resistance isn't small compared to R, then it will effect the overall resistance. The switches would be in series of 2R and would change the overall value. By having a larger resistance we can see a bigger voltage drop and a lower ouput.
    
 

Back up the work by emailing yourself.

 

 

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