Created and edited by Michael Parker
Email : parkem3@unlv.nevada.edu
Last updated : October 20 2021
Pre-Lab
- Back-up all of your previous work from the lab and the course.
- Go through tutorial 4 seen here.
The first task was to create a schematic of a NAND gate.
Next was to create a symbol for that gate.
The following task was to draft a schematic to test our symbol.
These are the results of that simulation.
The next step was to draft a layout of the NAND gate, extract it, and complete a LVS.
Lab Overview
The purpose of this lab is to design, layout, and simulate a CMOS NAND gate, XOR gate, and a Full-Adder.
Lab Procedures
Draft the schematics of a 2-input NAND gate, and a 2-input XOR gate using 6u/0.6u MOSFETs
NAND
XOR
Simulation schematic
Pulse Statement
Simulations
Draft a schematic of a full-adder using your gates
Layout of full-adder