The purpose of this lab is create a layout for the 10-bit DAC that was drafted and simulated in Lab #2.
Lab Procedures
Resistor Layout
For our layout we will be using 10k n-well resistors for all of our resistances.
In order to choose our length and width for our resistor we need to remember that,
R= RSquare * L/W
with the sheet resistance of an n-well resistor being about 800 ohms/square.
4.5 microns was chosen for our width and we were looking for a 10k ohm resistor which gave us the equation
10k = 800 * L/4.5u or L = 0.045/800
These results were divided by 2 in order to center the resistor about our origin.
The length and width of your n-well can be checked with a ruler by
selecting tools from the drop down menu or by pressing the shortcut K.
Click
at the beginning of the line you want to measure and then click at the
end, the ruler wil be present on your draft until you remove them with
the shoprtcut Shift+K
Schematic Layout
Once
you have the layout of your nwell resistor DRC the layout, save it, and
close it. I can now begin to layout our 10-bit DAC. I created a new
cell view
for this layout and instantiated my resistor i layed
out in the previous step. In order to allign my resistors in parallel
with each other i chose -90 as my x value and
alligned each of my later instantiated resistors to that point and varied my y values by 12 as shown below.
In total 31 resistors were needed to layout my schematic, 3 for each
bit of the 10-bit DAC and one leading to ground at the bottom. Once I
had
layed out the resistors I needed to connect 2 resistors in
series and one in parallel for each bit and connect each bitsbottom
with the next bits top with
metal on the metal 1 layer.
Pins
Now that I connected all of the bits and the ground
resistor together i needed to create pins for each of the inputs on the
bits (B0-B9) as well as
ground (gnd!) and the output of the circuit (Vout).
DRC and LVS
During
the entire design process I used DRC for every few design components
added to ensure that i was not violating any rules and to prevent
myself
from getting to far into the design before i was able
to correct any mistakes i had made. Below is an image of my final DRC
after the entire layout was complete.
Once
the DRC was completed with 0 errors I extracted my layout and compared
it with my schematic with an LVS. Below is the results of that test.
My design files (layouts and schematics) can be downloaded for refrence or examination by clickinghere.