Digital Integrated Circuit Design

EE 421L - Fall 2021

Lab 2

Author: Ryan Eclarinal

Email: eclarina@unlv.nevada.edu

Date Assigned: September 1, 2021

Due Date: September 8, 2021
 
Pre-Lab:
 
Pre-Lab Procedure:
First thing to do is download the lab2.zip then upload it to CMOSedu folder, then unzip it.
After unzipping, we need to add the following line "DEFINE lab2 $HOME/CMOSedu/lab2" to the cds.lib. When were done with those steps, we can start Cadence and open the lab2 library and click the schematic view of sim_ideal_ADC_DAC cell.
 

 
Launch the ADE and Run the simulation without changing anything and this is what we get:

 
Now, we need to use different simulations in order to understand how the input voltage(Vin) is related to B[9:0] and Vout and how to determine the LSB bit.
 
Using the formula: 1LSB = VDD/2^N
    where VDD = 5V and N = 10
       we get: 
                    1 LSB = 5V/2^10 = 4.88mV

4.88mV is the minimun voltage change for each step and with this information, we can change the properties of our voltage source.
 
Using 5mV as the voltage source will get this result.

Looking at the voltage steps we see that the voltage difference is equal to 4.88mV.
 
Let's run another simulation with a voltage source that is exactly 4.88mV. We need to change the amplitude and DC offset to 2.44mV to accomplish this and see the result.

This simulation verifies that the step size is indeed 4.88mV.
 
With the information that we gathered from performing the pre-lab, we can answer the following questions.
1. How is Vin related to B[9:0] and Vout?
Vin is an analog source that goes into the ADC, where it is converted into the binary number B[9:0] which is the 10-bit binary representation of Vin. The 10-bit binary number goes into the DAC to be converted into an analog output which is the Vout.
 
2. Provide, and discuss, simulation results different from the above to illustrate your understanding of the ADC and DAC.
The ADC receives an analog input which is the Vin and converts the input into binary code. The binary code will be the output of the ADC and received by the DAC as an input. The DAC takes the binary code and converts it to an analog waveform.

3. Explain how you determine the least significant bit (LSB, the minumum voltage change on the ADC's input to see a change in the digital code B[9:0]) of the converter.    
To determine the LSB, we use the formula: 1LSB = VDD/2^N
 
Lab2 Description:
For this lab, we will be implementing our own design of 10-bit DAC.
 
Lab2 Procedure:
1. We need to create a schematic and symbol of a 10K n-well resistor which is a voltage divider with three resistors and three pins representing the input, output and carry bit.

 
To create a symbol, after finishing the schematics, click the "Create" tab, then "cellview" and "from cellview" and this is what we get:

 
Now that we created a symbol, we can use this to modify the schematic of a 10-bit DAC cell by connecting 10 of them together. After we finished with the schematics, we need to create a new symbol for our 10-bit DAC.

 

 
2. Testing the 10-bit DAC design.
Hand calculations:

 
In finding the total resistance, ground all DAC inputs except B9 then connect B9 to a pulse source (0 to VDD) and show, and predict using 0.7RC, the delay the DAC has driving a 10 pF load.

 
Result that we got:


3. Simulations to verify if our design functions correctly.
We need to copy the schematic cellview "sim_Ideal_ADC_DAC to a cell "sim2_Ideal_ADC_DAC" and replace the ideal DAC with the one we just designed.

 
When running it after we replace the DAC with our design gives us this result. We can see that we got the same result as the pre-lab for our simulation.

 
4.Now, we will show what will happens if the DAC that we designed drives a load(both R, C and R/C).

a. Applying a resistive load of 10K.

 

From this simulation, the DAC and the 10K load became a voltage divider and half the output to 2.5V.
 
b. Applying a capacitive load of 10pF.

 

For this simulation, the output smoothes out and it lags behind the input.
 
c. Applying a both resistive load of 10K and a capacitive load of 10pF.

 

For this simulation, the output also smoothes out and nearly half the input voltage and it also lags from the input.
 
Question:
In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). Discuss what happens if the resistance of the switches isn't small compared to R.

If the switches were not small, we would have an additional resistance added to the two 10K resistors and this would increase the total output resistance and will cause a greater voltage drop of the Vout.

Backing up:
 
Perform a regular back up of my work by making a zip file and uplaod it to my Google Drive.

 

 
This concludes Lab 2.    

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