Digital Integrated Circuit DesignEE 421L - Fall 2021
Final Project
Author: Ryan Eclarinal
Email: eclarina@unlv.nevada.edu
Due Date: November 24, 2021
Final Project: Register file
Project Description:
Design a register file that uses 8 bit word and contains 32 words.
Components for the Project:
SRAM cell
8-bit word SRAM
32 bit Array
5 input NAND gate
Row Decoder
Register File
SRAM Cell:
A
pair of weakly cross coupled inverters hold the state, while a pair of
access transistors read and write the states in the 6-transistor SRAM
cell. The write operation is performed by feeding the desired value and
complement into the D and Di bit lines, then raising the WL word line.
The data is overpowered with the help of cross coupled inverters. The
two bit lines' pre-charging is set to high and then left to float. When
a word is raised, the Di is dragged down, indicating the data's value.
The main issue of the SRAM is to make sure that the circuit that holds
the state is both weak enough to ensure the write operation by
overpowering the previously stored value and powerful enough to keep it
during the read operation.
Schematic:
Symbol:
Layout:
Extracted Layout:
DRC:
LVS: Showing the net-lists matched.
Simulation:
Results:
Result shows that when WL is high, the value of D is stored.
8-bit WORD SRAM:
The next component is an 8 bit word SRAM that consist of 8 SRAM cell that was designed previously.
Schematics:
Symbol:
Layout:
Extracted Layout:
DRC:
LVS: Showing the net-lists matched.
Simulation:
Results:
As seen on the result, same as single cell SRAM, when WL is high, the value of D is stored.
32-bit Array:
The
3rd component is the 32-bit Array. We can make this by instantiating
the 8-bit word cell, 32 times. This array will store the memory for the
32 8-bit words.
Schematics:
Symbols:
Layout:
Zoom of the layout:
Extracted Layout:
Zoom of extracted layout:
DRC:
LVS: Showing the net-lists matched:
5 Input NAND Gate:
We
need to create a 5 input NAND gate that we will need for the Row
Decoder, which is the last component to build the Register File.
Schematics:
Symbol:
Layout:
Extracted Layout:
DRC:
LVS: Showing the net-lists matched.
Simulation:
Results:
Results shows that when all inputs are not high, the output is "1". When all inputs are high, the output is "0".
Row Decoder:
The
final component that we need for the Register File is a Row Decoder. A
Row Decoder is a combinational logic circuit that converts coded input
to coded output. When you are putting an address, it will select 1 out
of 32 rows.
Schematics:
Symbol:
Layout:
Zoom of layout:
Extracted Layout:
Zoom of extracted layout:
DRC:
LVS: Showing the net-lists matched.
Simulation:
Results:
When selecting ABCDE = 11111, Row<31> turns on.
When selecting ABCDE = 11110, Row<30> turns on.
When selecting ABCDE = 11101, Row<29> turns on.
This shows that the Row Decoder is working properly.
Register File:
We
now have all the components that we need to design the Register File.
To do this, we created a new cell and instantiated the Row Decoder and
the 32 bit Array and connect the RL with a wide wire.
Schematics:
Symbol:
Layout:
Extracted Layout:
Zoom of layout:
DRC:
LVS: Showing the net-lists matched.
Simulation:
Results:
The
Register File is working accordingly. When A0 is high(1), address
11110 is being called which writes to R<30> and then it follows
D<0>. When A0 is low<0>, address 11111 is being called
which writes to R<31> which follows D<0>.
Final Lab Project Files
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