Lab 6 - EE 421L 

Authored by Charlene Drake

Email: drakec2@unlv.nevada.edu

October 20, 2021 

Prelab

For this prelab we were to follow along with Tutorial 4 where we would design a NAND gate. 

After copying over the library from tutorial 3, we were ready to design the schematic for the NAND gate which consisted of two PMOS's and two NMOS's which we designed in previous tutorials.
   

From the schematic we could then create the symbol for the NAND which was used in the schematic for simulation.



After simulating we get the following results.


Next we needed to layout and extract the NAND gate.

     

To make sure our layouts followed design rules and matched with our schematics we need to DRC and LVS.





Lab Description

2-Input NAND Gate:

To design our 2-input NAND gate we were able to use the same design from the prelab. The only difference was we needed to add our initials to our symbols.
   

To verify that our NAND gates were operating correctly and following the truth table we needed to simulate. The following values were assigned to the pulse voltages.
   

 

As you can see the results of the simulation match our truth table.

Now we were ready to layout and extract our design. From the layout we designed in the prelab, we needed to adjust the measurements of the PMOS since we originally used 12u/600n and in our schematic the PMOS was actually 6u/600n.
 

With our layout and extraction complete we were ready to DRC and LVS.


 



2-Input XOR Gate:

To design the 2-input XOR gate we were given an example of how the schematic should look and we just needed to follow it.
 

Next, we were ready to simulate and verify that our gate was working properly by comparing it to our truth table.

The following values were assigned to the impulse voltages.
   

   
As you can see, the results of the simulation match those in the truth table.

Now we were ready to layout and extract.
 

To make sure our layout matched design rules we DRC and to verify that we properly layed out the design we LVS.



Testing Gates:
To double check that our gates were operating correctly we design the following schematic which included the NAND and XOR gates we just designed and an inverter designed in a previous tutorial.
    
As you can see there are a few glitches in the waveforms. This is because the logic signals cannot  change instaneously. During the 1n rise and fall time the signals transition from "1" and "0" and during this transition the it is unknown whether the MOSFET is on and off.

Full Adder:

To draft the full adder we use the symbols previously created in the lab to design the following schematic.


We also create the following symbol.


With our symbol created we are ready to design the schematic for simulation and assign the following values to

the pulse voltages.
       

 

Next we are able to layout our design. In order to do so we needed to instantiate the layouts we had previously created for our NAND and XOR gate.


With our layout complete we are able to extract our designs.


To verify our layout follows design rules we DRC and to make sure it matches our schematics we LVS.