Lab 5 - EE 421L 

Authored by Charlene Drake

Email: drakec2@unlv.nevada.edu

October 6, 2021

Prelab

For the prelab we were required to follow Tutorial 3 to design a CMOS inverter using our PMOS and NMOS created in previous tutorials. 

Layout and Extracted views of Inverter:

Once we had our layout complete we were able to DRC and then extract. With the extracted view we could LVS and compare the netlist with that of the schematic. 

With our netlists matching, we were then ready to simulate. 

Lab description

12u/6u Inverter:

For this inverter we were able to use the inverter created previously in the prelab with a few minor adjustments such as adding text to the symbol.

Inverter schematic and symbol:

  Layout and Extracted views:

Clean DRC:

Matching Netlists:

48u/24u Inverter:

For the second inverter we needed to design, once again we used the same schematic used for the 12u/6u inverter, but this time there was a multiplier of 4.

Inverter Schematic and Symbol:

Layout and Extracted views:

Clean DRC:

Matching Netlists:

With the designs of both inverters complete, we were ready to start simulating.

12u/6u Inverter Simulation Schematic:

Spectre Simulation:

UltraSim Simulation:

Even though the faster speed of UltraSim has affect on the accuracy, when comparing the two simulations we do not see much of a difference.

48u/24u Simulation Schematic:

Spectre Simulation:

UltraSim Simulation:

Design files can be found here.

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