Lab 3 - EE 421L 

Authored by Charlene Drake, 

Email: drakec2@unlv.nevada.edu

September 15, 2021

 Prelab:

  The first thing needed to be done for this lab was to complete which Tutorial 1. In this tutorial we designed a 10K n-well resistor that was used in a voltage divider.

To determine the measurements of our 10K  resistor we first referenced the MOSIS for the design rules. Since our sheet resistance needed to be 800Ω per square for the n-well we used and the minimum width needed to be 3.6µm, we could plug those 2 into the following equation with the resistance to find the length:

l = R*w / Rsquare = 10k * 3.6µm / 800Ω per square = 45µm

As you can see, the desired length of the resitor is 42µm but since we were following along to Dr. Baker's tutorial we used 56.1µm and 4.5µm for the width.

Lab Procedures

The following is the schematic of the 10-bit DAC that we designed in lab2.

In order to design our 10-bit DAC layout we used the 10K n-well resistor from Tutorial 1. Since 3 n-well resistors makeup 1 bit, we needed a total of 31 n-well resistors to account for the 10-bits plus gnd.

,y}w_cI~UELl

Once we extracted our design we were able to run the DRC.

The last step to make sure the netlists of the schematic and the layout matched was to run the LVS.

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