Lab 3 - EE 421L 

Damian Aceves-Franco

acevesfr@unlv.nevada.edu

09/14/2021

         

Layout of a 10-bit digital-to-analog converter (DAC)

               

Prelab 

       
The rest of the tutorial 1 involves makeing an N-Well resistor (10K each)  in layout and  and building the flowing circuit in schematic layout and comeparing this schematic to the one in layout by the use of LVS
       
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st1.JPG
Now the layout and LVS ( if the net-list match)  we were sucessful in making sure they are the same circuits.
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st2.JPG
                 
Extrating the layout shows us the value of the N-Well resistance I made.
               
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st8.JPG
                 

                   

*******************************************************************************************************************************************

Lab 

         

This lab will focus on the layout of the 10-bit DAC you designed and simulated in Lab 2

**********************************************************************************************************************************************

         
Work
                       
Use the n-well to layout a 10k resistor as discussed in Tutorial 1
- lets say the width of the 10K resistor is 4.5um and we want to find out with the lenght would be with we do this by
using the formula  
                     
R= Rper-square*    L  
                           W
                   
we know by the table provied  here the Rpersquare is about 855 or about 800 ohms/square. So 10K= 800 * L/4.5 => L= 56.25+0.3 ~57
                                                     
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st9.JPG
                             
Use this n-well resistor in the layout of your DAC
           
This the schematic view of the circuit.
                                         
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st3.JPG
                 
after making it into a symbole we get this
                       
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st11.JPG
                   
As we did in Lab 2

             
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st10.JPG
                       
We place the 10K N-well I this configuration to get the same type of circuit as in schematic view and making them have the proper spacing of 5.40um between them. As well we must name the pin the same and place them were they need to be and wire everything up with metal1.
                         
-http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st4.JPG


after doing we DRC and LVS it as we did in the prelab to make sure everything lines up and its working properly

             http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st13.JPG

     http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st14.JPG
http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st5.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st6.JPG
               
Backing up the work



http://cmosedu.com/jbaker/courses/ee421L/f21/students/acevesfr/Labs/Lab%203/st12.JPG

Below are the files for this lab
ZipFile.

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