Lab 7- EE 421L Fall 2020 

Authored by: Nathan Pina
Email: pinan1@unlv.nevada.edu
Due Date: 11/18/20

  

Lab description:

Using buses and arrays in the design of word inverters, muxes, and high-speed adders

Pre-Lab:

- Back-up all of your work from the lab and the course.
- Go through Cadence Tutorial 5 seen here.

31 Stage Ring Oscillator (Schematic and Symbol)
lab7/fig1.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig1.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig2.JPG

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31 Stage Ring Oscillator (Layout and Simulation)

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Main Lab Work:
The lab is split into several sections:
a.) Schematics and simulations of a 4-bit Inverter gate using 6u/0.6u MOSFETs (both NMOS and PMOS)
b.) Schematics and simulations of a 8-bit NAND, NOR, AND, inverter, and OR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)
c.) Schematics and simulations of a 2-to1 DEMUX/MUX (8-bit wide word version as well)

d.) Schematic and symbol for full adder 

e.) Schematics, layouts, and simulations of a 8-bit full-adder circuit

1.) 4-bit Inverter (Schematic and Symbol)

file:///C:/Users/Nathan/Desktop/lab7/fig9.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig10.JPG

The 4-bit input of the four inversters is condensed into an equivalent circuit with  the 4-bit input and output named b<3:0> and bi<3:0>  respectively.

file:///C:/Users/Nathan/Desktop/lab7/fig11.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig12.JPG

This is the simulation schematic we’ll be using to test the cirucit, 100fF on the 4th bit, 500fF on the 3rd bit, 1pF on the 2nd bit, and a no capacitor on the 1st bit.

2.)  8-bit NAND, NOR, AND, inverter, and OR gates (Schematics and Simulations)

8-bit NAND Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig13.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig14.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig15.JPG

8-bit NOR Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig16.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig17.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig18.JPG

8-bit AND Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig19.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig20.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig21.JPG

8-bit Inverter Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig22.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig23.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig52.JPG

8-bit OR Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig24.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig25.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig26.JPG

*All simulations were done simultaneously to reduce the amount of schematics needed. All 8-bits were oberserved for each gate.

file:///C:/Users/Nathan/Desktop/lab7/fig27.JPG

8-bit NAND Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig30.JPG

8-bit NOR Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig32.JPG

8-bit AND Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig29.JPG

8-bit Inverter Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig28.JPG

8-bit OR Gate:

file:///C:/Users/Nathan/Desktop/lab7/fig31.JPG

3.) 2-to1 DEMUX/MUX (Schematic, Symbol and Simlations)

file:///C:/Users/Nathan/Desktop/lab7/fig33.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig34.JPG

file:///C:/Users/Nathan/Desktop/lab7/fig35.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig36.JPG

MUX: When the input of S is high, the output Z will follow A. When the input of S is low, the ouput Z will follow B.

DEMUX: When the input of S is high, A will follow the ouput Z. When the input of S is low, B will follow the output Z. Z will remain at its last known value of either A or B is not following it.

3.) (8-bit) 2-to1 DEMUX/MUX (Schematic, Symbol and Simlations)

file:///C:/Users/Nathan/Desktop/lab7/fig37.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig38.JPG

file:///C:/Users/Nathan/Desktop/lab7/fig39.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig40.JPG

**DEMUX Simulation

file:///C:/Users/Nathan/Desktop/lab7/fig41.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig42.JPG

4.) Full Adder (Schematic and Symbol)

file:///C:/Users/Nathan/Desktop/lab7/fig43.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig44.JPG

5.) 8-bit Full Adder (Schematic, Symbol, Simulations, Layout)

file:///C:/Users/Nathan/Desktop/lab7/fig45.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig46.JPG

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file:///C:/Users/Nathan/Desktop/lab7/fig48.JPGfile:///C:/Users/Nathan/Desktop/lab7/fig48_b.JPG

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*Zoomed in view of adder

file:///C:/Users/Nathan/Desktop/lab7/fig51.JPG

Lab Backup
After I completed this lab, I made sure to back up all files (schematics, simulations, screenshots etc.) into a zip file and upload to my Google Drive

file:///C:/Users/Nathan/Desktop/lab7/fig53.JPG