Lab 7- EE 421L Fall 2020
Authored by: Nathan PinaMain Lab Work:
The lab is split into several sections:
a.) Schematics and simulations of a 4-bit Inverter gate using 6u/0.6u MOSFETs (both NMOS and PMOS)
b.) Schematics and simulations of a 8-bit NAND, NOR, AND, inverter, and OR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)
c.) Schematics and simulations of a 2-to1 DEMUX/MUX (8-bit wide word version as well)
d.) Schematic and symbol for full adder
e.) Schematics, layouts, and simulations of a 8-bit full-adder circuit
1.) 4-bit Inverter (Schematic and Symbol)
This is the simulation schematic we’ll be using to test the cirucit, 100fF on the 4th bit, 500fF on the 3rd bit, 1pF on the 2nd bit, and a no capacitor on the 1st bit.
2.) 8-bit NAND, NOR, AND, inverter, and OR gates (Schematics and Simulations)
8-bit NAND Gate:
8-bit NOR Gate:
8-bit AND Gate:
8-bit Inverter Gate:
8-bit OR Gate:
*All simulations were done simultaneously to reduce the amount of schematics needed. All 8-bits were oberserved for each gate.
8-bit NAND Gate:
8-bit NOR Gate:
8-bit AND Gate:
8-bit Inverter Gate:
8-bit OR Gate:
3.) 2-to1 DEMUX/MUX (Schematic, Symbol and Simlations)
MUX: When the input of S is high, the output Z will follow A. When the input of S is low, the ouput Z will follow B.
DEMUX: When the input of S is high, A will follow the ouput Z. When the input of S is low, B will follow the output Z. Z will remain at its last known value of either A or B is not following it.
3.) (8-bit) 2-to1 DEMUX/MUX (Schematic, Symbol and Simlations)
**DEMUX Simulation
4.) Full Adder (Schematic and Symbol)
5.) 8-bit Full Adder (Schematic, Symbol, Simulations, Layout)
Lab Backup
After
I completed this lab, I made sure to back up all files (schematics,
simulations, screenshots etc.) into a zip file and upload to my Google
Drive