Lab

Lab 6- EE 421L Fall 2020

Authored by: Nathan Pina
Email: pinan1@unlv.nevada.edu
Due Date: 10/21/20

Lab description:

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Pre-Lab:

- Back-up all of your work from the lab and the course.
- Go through Cadence Tutorial 4 seen here.

NAND Gate Design (Schematic and Symbol)

NAND Gate Design (Layout and Extracted)

NAND Gate Simulation

**Note: Although the layout will pass the LVS, the PMOS devices found in the layout will be different sizes compared to those in the schematic. In order to fix this, you must compare the device sizes by changing the LVS rules (NCSU > Modify LVS Rules > Compare FET Parameters). Below is the message after the neccessary changes are made.

Main Lab Work:
The lab is split into two main sections:
a.) Schematics, layouts, and simulations of a 2-input NAND gate using 6u/0.6u MOSFETs (both NMOS and PMOS)
b.) Schematics, layouts, and simulations of a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)
c.) Schematics, layouts, and simulations of a full-adder circuit

1.) 2-input NAND Gate
- This NAND gate will be heavily based on the design and simulations from tutorial 4 however, the PMOS and NMOS devices will be set to 6u/0.6u.
- Symbol views are commonly used symbols (not boxes!) for these gates with my initials in the middle of the symbol
- All layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
- Gate inputs, outputs, vdd!, and gnd! are all routed on metal1

NAND Gate Design (Schematic and Symbol)

NAND Gate Design (Layout and Extracted)

NAND Gate Simulation

The simulations were done using different pulse inputs that were given varying pulse widths in order to cover all 4 possible inputs (00,01,10,11). The NAND gates functions as expected, with the gate output being high for all inputs expect for when the inputs are both high.
The "glitches" in the simulation output occur during the transition period of either input since during the those rise and fall times the inputs are not exactly "high" or "low".

2.) 2-input XOR Gate
- This XOR gate will be heavily based on the design and simulations from tutorial 4 and the CMOSedu textbook, however, the PMOS and NMOS devices will be set to 6u/0.6u.
- Symbol views are commonly used symbols (not boxes!) for these gates with my initials in the middle of the symbol
- All layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
- Gate inputs, outputs, vdd!, and gnd! are all routed on metal1

XOR Gate Design (Schematic and Symbol)

XOR Gate Design (Layout and Extracted)

XOR Gate Simulation

The simulations were done using different pulse inputs that were given varying pulse widths in order to cover all 4 possible inputs (00,01,10,11). The XOR gates functions as expected, with the gate output being high when both inputs are different and low when both inputs are the same.
The "glitches" in the simulation output occur during the transition period of either input since during the those rise and fall times the inputs are not exactly "high" or "low".

3.) Full-Adder
- PMOS and NMOS devices will be set to 6u/0.6u.
- Symbol views are commonly used symbols (not boxes!) for these gates with my initials in the middle of the symbol
- All layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
- Gate inputs, outputs, vdd!, and gnd! are all routed on metal1

Full-Adder Design (Schematic and Symbol)

Full-Adder Design (Layout and Extracted)

Full-Adder Simulation

The simulations were done using different pulse inputs that were given varying pulse widths in order to cover all 4 possible inputs (00,01,10,11). The full-adder functions as expected, following the truth table seen above.
The "glitches" in the simulation output occur during the transition period of either input since during the those rise and fall times the inputs are not exactly "high" or "low".

Lab Backup
After I completed this lab, I made sure to back up all files (schematics, simulations, screenshots etc.) into a zip file and upload to my Google Drive