Lab

Lab 5- EE 421L Fall 2020

Authored by: Nathan Pina
Email: pinan1@unlv.nevada.edu
Due Date: 10/07/20

Lab description:

Design, layout, and simulation of a CMOS inverter

Pre-Lab:

-Back-up all of your work from the lab and the course.
-Go through Tutorial 3 seen here.

Inverter Design (Schematic and Symbol)

Inverter Design (Layout and Extracted)

Inverter Simulation

Main Lab Work:
The lab is split into two main sections:
a.) Schematics, layouts, and simulations of 12u/6u inverter
a.) Schematics, layouts, and simulations of 48u/24u inverter

1.) 12u/6u Inverter
This inverter is heavily based on the design and simulations from tutorial 3. Some important design notes for this inverter are as follows:
- Width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u
- Power is run on the top of the cell via metal1 and ground is run on the bottom of the cell also via metal1
- Power (vdd!) is connected to the n-well using the ntap cell
- Ground (gnd!) is connected to the p-substrate using the ptap cell
- 4 pins: A, Ai, vdd!, and gnd!

Inverter Design (Schematic and Symbol)

Inverter Design (Layout and Extracted)

Inverter Simulation (12u/6u)
For the following simulations, the inverter operated while driving a capacitive load uising the following values: 100 fF, 1 pF, 10 pF, and 100 pF.
The simulations were also done using UltraSim, a fast SPICE simulator for larger circuits at the cost of accuracy. Since this circuit is neither very large or complex, this will give similar results to its SPECTRE counterpart.

Top Left: 100f capacitive load
Top Right: 1p capacitive load
Bottom Left: 10p capacitive load
Bottom Right: 100p capacitive load

Results: The inverter will function correctly at capacitive loads under 10pF. As the capacitors increase in size, the time it takes to charge and discharge them also increases. For example, in the above instance, at 100pF the output was not able to go "low" when the input was "high" since it takes more time for the capacitor to discharge.

2.) 48u/24u Inverter
Some important design notes for this inverter are as follows:
- Power is run on the top of the cell via metal1 and ground is run on the bottom of the cell also via metal1
- Power (vdd!) is connected to the n-well using the ntap cell
- Ground (gnd!) is connected to the p-substrate using the ptap cell
- 4 pins: A, Ai, vdd!, and gnd!

Inverter Design (Schematic and Symbol)

Inverter Design (Layout and Extracted)

Inverter Simulation (48u/24u)
For the following simulations, the inverter operated while driving a capacitive load uising the following values: 100 fF, 1 pF, 10 pF, and 100 pF.
The simulations were also done using UltraSim, a fast SPICE simulator for larger circuit at the cost of accuracy. Since this circuit is neither very large or complex, this will give similar results to its SPECTRE counterpart.

Top Left: 100f capacitive load
Top Right: 1p capacitive load
Bottom Left: 10p capacitive load
Bottom Right: 100p capacitive load

Results: Compared to the smaller 12u/6u version of this design, the inverter can handle bigger capacitive loads and improved in all four test scenarios. Both the 100fF and 1pF load test results were more refined and showed a bigger distinction between the "high" input and "low" output. While not perfect, the 10pF test showed noticeable improvement and gradually reached the correct value toward the end of the input pulse. Finally, the 100pF load also showed improvement with a bigger inverter size, but not enough to warrent its use. The inverter still does not work correctly under a capacitor of this size and would need to increase in size even further to accomodate it.

**All schematics, layouts, symbols, and simulations can be found here.

Lab Backup
After I completed this lab, I made sure to back up all files (schematics, simulations, screenshots etc.) into a zip file and upload to my Google Drive