Lab

Lab 3- EE 421L Fall 2020

Authored by: Nathan Pina
Email: pinan1@unlv.nevada.edu
Due Date: 9/16/20

Lab description:

Layout of a 10-bit digital-to-analog converter (DAC)

Pre-Lab:
-Back-up all of your previous work from the lab and the course.
-Finish Tutorial 1

First portion of the pre-lab involved finishing tutorial 1 and creating a 10k resistor and resistive divider along with it. Tutorial 1 can be found here.

Resistor was made to be as close to 10k as possible. Following the tutorial, I was able to achieve a resistance of 10.21k. Once this made, I was able to create a layout of the resistive divider.

In cadence, you must instantiate 2 seperate resistor models and connect them through the metal 1 layer (blue rectangles seen above). Once the necessary connections are made, extract the layout and perform a LVS check to ensure matching net-lists.

Main Lab Work:
The main portion of the lab involved implementing a 10k n-well resistor into the layout of the DAC created in lab 2.

1.) Selection of Length and Width
In order to aquire the 10k value of the resistor, you must input the appropriate dimensions that follow the MOSIS design parameters. For this resistor, the following values were chosen:

        Minimum Width: 4.5 microns
        Minimuim Length: 56.1 microns
        Sheet Resistance: 800 ohms/square

The sheet resistance was given from cadence files while the width was determined by the 12 lamba or 0.3um design requirement. The length was chosen by adjusting the equation for finding the resistance of the resistor (R=Rsquare * (L/W)).
The new equation for the length of the resistor is as follows:

                       L = (R*W) / Rsquare
                        L = Length
                        R = Resistance
                        W = Width
                        Rquare = Sheet Resistance

The measurements that were taken above were done using the built in ruler in cadnece. This can be accessed by pressing "k" or using the "Tool" drop down menu and selecting "Create Ruler".

2.) Layout of the DAC
In order for the new DAC layout to function with an input of 10 bits, I needed to instantiate a total of 31 resistors. These resistors will all share the same X position on the layout grid but differ in Y position. They were also positioned 5.4 microns apart from each so that no design rules were broken. As before, each of these resistors are valued at 10.21k and connected to each other through the metal 1 layer.

The left image is the full 31 resistor layout with all connections made. The right image is a zoomed in portion of the layout, displaying the connections between each of the resistors.

3.) DRC and LVS Check
Once the layout was fully completed, a final DRC check was done.

The layout was then extracted and then once again was put through both a DRC and LVS check.

The full design dirctory, including the layouts, schematics, and simualtions, can be found here.

Lab Backup
After I completed this lab, I made sure to back up all files (schematics, simulations, screenshots etc.) into a zip file and upload to my Google Drive.