Lab 5 - EE 421L 

Authored by Michael Nguyen

October 03, 2020

Lab description

Pre-lab work

• Back-up all of your work from the lab and the course.
• Go through Tutorial 3 seen here.

Lab Work:

• Draft schematics, layouts, and symbols for two inverters having sizes of: 
• 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
• 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET)
• Your schematics should have two pins, e.g., A and Ai
• Your layouts should have 4 pins: A, Ai, vdd!, and gnd! (note how lowercase letters are used for power and ground)
• Your lab reports should document your efforts and results including showing that the extracted layouts and schematics LVS correctly
• Zip up these cells in a directory: lab5_jeb
• Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
• Comment, in your report, on the results
• Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations 

Since the 12u/6u CMOS inverter was designed, DRC, and LVS in the prelab, this will only show the simulation of the 12u/6u inverter with varying capactior values.

Schematic

Spectre Simulation                                                                                    UltraSim Simulation

The two simulation showed unnoticable discrepancy since it's a small circuit. At smaller capacitor values 100fF to 1pF the inverter performs correctly, but at bigger capacitors values 10pF to 100pF made the inverter perform incorrectly.

CMOS Inverter Design (48u/24u):

Schematic                                                                   Symbol

 Layout                                                                            Extracted

 DRC                                                                                                          LVS

 48u/24u Inverter Simulation

Schematic

 Spectre Simulation                                                                                             UltraSim Simulation

 Same thing as the 12u/6u inverter the two simulation shows unnoticable discrepancy, however there are some differences in this. At the 100fF to 1pF the inverter  still performs correctly, but at 10pF it also performed relatively correctly and at 100pf it doesn't appear to perform correctly.