Lab 7 - ECE 421L 

Quinton Micheau

10/31/2020

micheauq@unlv.nevada.edu

Lab 7

We will begin by going over Tutorial 5. This tutorial covers how to layout a ring oscillator which will be used in future projects.

Schematic, Simulation Output and Layout of the ring oscillator

LVS and proof that we are simulating the extracted version.

Lab 7
The first task is to create a symbol for a 4-bit inverter using a bus line and simulate.

Schematic	Simulation Results

Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
Provide a few simulation examples using these gates.

8-bit NAND Gate
Schematic	Simulation Results

8-bit AND Gate
Schematic	Simulation Results

8-bit OR Gate
Schematic	Simulation Results

8-bit NOR Gate
Schematic	Simulation Results

8-bit Inverter
Schematic	Simulation Results

2-1 MUX/DEMUX

Below is the schematic and output of a MUX Gate

Schematic	Output Operation

8-bit MUX

Schematic	Ouput

DEMUX

Schematic	Output

Below is the Schematic, Layout, Extracted Layout, LVS and Simulation of an 8 bit Full Adder.

Single Bit Adder
Schematic		LVS
Layout

Layout
Close up of Layout Section (Note: Total length of the layout is 1050 um or just barely 1mm)
Close up of Layout Section
Height Dimension of Layout (20 um Smaller than "thinner" than last design)
Extracted view of Inputs An and Bn highlighted
Extraced view of the carry-over bit
LVS

Bit Addition 

The following operation will be performed by the circuit:

And this is what we get in the simulation!

Schematic	Output

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