Lab 6 - ECE 421L 

Quinton Micheau

10/19/2020

micheauq@unlv.nevada.edu

Lab 6

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

To start, Tutorial 4 goes over the basics of laying out and drawing the schematic of a NAND gate.

Schmatic	Layout
Setup	Results

Schematic	Layout
Simulation

Schematic	Layout
Simulation

Schematic
Simulation results with Truth Table
Layout
LVS

Symbol

Glitches

Recall from the above simulation outputs that were some irregularities in the XOR gate seen below. Notice the downwards spike in between the output highs.  Ideally, we would like a smooth output.

Zooming in on the glitch

In an attempt to smooth out the signal, inverter buffers were inserted between the input and the XOR gate.

12u Inverter Buffer

48u Inverter Buffer

As see above, the glitching does apper to fade with the input coming from another logic gate. 

Now, taking the idea a bit further...

Unfortunately, it appears as though since the gates cant change instantaneously, there will always be a moment between switching where the output of the XOR2 gate will drop to zero. Even if it is less than a nanosecond.

 Lab6.zip

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