Lab 5 - ECE 421L 

Quinton Micheau

Today's date: 10/4/2020

micheauq@unlv.nevada.edu

Lab 5

Lab description:

This laboratory covers the design of the schematic and layout of an inverter using MOSFETs. Tutorial 3 covers the material presented here.

• Draft schematics, layouts, and symbols for two inverters having sizes of: 
• 12u/6u
• 48u/24u
  

12u/6u	48u/24u

Simulations

The following schematic will be simulated. The capacitance will increase slightly with each increment simulation and the results are shown below the schematic.

100 fF	1 pF
10 pF	100 pF

Animation showing progressive increase in capacitance:

The following schematic will be simulated. The capacitance will increase slightly with each increment simulation and the results are shown below the schematic.

100 fF	1 pF
10 pF	100 pF

Animation showing progressive increase in capacitance:

Lab5.zip

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