Lab 8 - EE 421L 

Authored by Peter Kim

kimj98@unlv.nevada.edu

12/2/2020

 

Prelab:

-    Back-up all of your work from the lab and the course
-    Go through Cadence Tutorial 6 seen here
-    Read through the lab in its entirety before starting to work on it
     

http://cmosedu.com/jbaker/courses/ee421L/f20/students/kimj98/lab8/lab8.htm

         
         
       
         
           
         

Lab Report:


Test chip specification:
-    PIN 20 - GND
-    Each circuit should have its own power.

Tesh chip should include the following:
-    One, or more course project
-    A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
-    NAND and NOR gates using 6/0.6 NMOSs and PMOSs
-    An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
-    Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each devices connected to bond pads (7 pads + common gnd pad)
-    A 25k resistor implemented using the n-well
-    Using the 25k resistor and 10k resistor, implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor)


31-STAGE RING OSCILLATOR with a buffer for driving 20pF off-chip load
- Measure at pin 1 for output oscillation
   
pin 1Osc_out
pin 2VDD_Osc
pin 20GND
     
Schematic & Symbol & layout 




         
         
         
INVERTER
- Apply Input at pin 5, measure the voltage at pin 3.
             
pin 3OUT_Inverter
pin 4VDD_Inverter
pin 5IN_Inverter
     
Schematic & Symbol & layout
   
                   
         
             
           
NAND GATE
- Apply inputs to pin 8 & pin 9, measure the output at pin 6.
   
pin 6OUT_NAND
pin 7VDD_NAND
pin 8A
pin 9B
     
Schematic & Symbol & layout
   
         
     
         
       
         
NOR GATE
- Apply inputs to pin 12 & pin 13, measure output at pin 10
     
pin 10Out_NOR
pin 11VDD_NOR
pin 12A
pin 13B
     
    
     
   
       
       
       
PMOS
- Apply VDD to pin 14, Apply VSG and measure the drain for operation
       
pin 14Bulk
pin 15Source
pin 16Gate
pin 17Drain
       
Schematic & Symbol & layout
         
         
     
         
         
       
VOLTAGE DIVIDER
- Apply Vin at pin 18 and measure the output at pin 19
     
pin 18IN
pin 19OUT
         
Schematic & Symbol & layout
        


       
       
         
             
NMOS
- Apply VGS and measure the drain for operation
     
pin 21Drain
pin 22Gate
pin 12Source
       
Schematic & Symbol & layout
     
     
             
             
               
               
DIGITAL RECEIVER
- Apply differential inputs to pin 26 & pin 27 and measure at pin 24 for output
       
pin 24OUT
pin 25VDD
pin 26Vinn
pin 27Vinp
         
Schematic & Symbol & layout
GO TO PROJECT REPORT
         
         
             
FLYBACK SPS CONTROLLER CHIP
- Apply VDD at pin 37 and 1.24V to pin 35, measure pin 36 for oscillation
     
pin 35Vfb
pin 36VOUT
pin 37VDD
       
Schematic & Symbol & layout

 


         
           
             
               
                 
CHIP SCHEMATIC

         
CHIP LAYOUT (click for a larger view)

       
LVS
        
       
         
PIN LIST

         
       
Click here to download chip4_f20.zip
         
END OF LAB 8
           

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