Lab

Lab 3 - EE421L

Authored by Rhyan Granados

9/9/20

Goal

The oobjective of this lab is to draft a layout of the 10-bit DAC.

Prelab

I backed up my work for Lab 2 as shown in the Lab 2 report.

I finished tutorial in order to complete an assignment for HW3 for EE421, below is a picture of the layout that I drafted with the help of Cadence Tutorial 1

The Lab

1) Utilizing layout of 10k Resistor using N-Well from Tutorial 1

How to select width and length of resistor by referencing info from MOSIS

For the C5 process, the sheet resistance is approximately 800 ohms/square as we can see below. Additionally, the minimum width is 12λ, and one lambda is worth 0.3 μm; 12λ=3.6μm. To calculate resistance in a layout we use the formula listed to the right of the sheet resistance table.

Using the formula above, we have R=10k ohms, Sheet Resistance= 800 ohms/square, and minimum width as 3.6μm. So, Length= (10k ohms * 3.6μm)/(796 ohms/square)=45.23 μm. To find our lambda value, we simply take our length and divide it by 0.3 μm when we do that we get 150.7666 or 151 lambda.

2) Use this n-well resistor in the layout of your DAC

Discuss, in your lab report, how the width and length of the resistor are measured

Now we will draft our 10k ohms n-well resistor with the dimensions we calculated: 45.3 μm length with a width of 3.60 μm. So the first step is using the n-well layer and creating an arbitrary
rectangle and then going to it's properties and entering our dimensions. Once our dimensions have been entered we will test to make sure it's DRC clean, and it is.

To measure the width and length, we go to tools->create a ruler->then click where you want to start measuring then click where you want it to end.

Now we will create connectors for our resistors. We'll go to Create->Instance or click i. Then we'll go to NCSU_TechLib_ami06 and find ntap and attach one to the left and the right end of the resistor. Make sure that the ntap connects just right, no overlap or underlap. From there we go to Options->Display, look for Display Levels and set the stop to 10.

Then we'll create pins for the left and right connectors. Change the layer to metal1 (drw), Create->Pin, draw a rectangle over the ntap, and label the left one L and the right one R (Make sure Display Terminal Name under label is check marked; otherwise, you won't see the labels). And as a final step in creating our resistor, we'll go to the res_id layer (make sure it's drw), create a rectangle precisely over our green rectangle, then run DRC.

To check that our resistor value is actually 10k ohms, we go to Verify->Extract and hit OK without changing anything. This will spawn a new cell within our 10k resistor file called "extracted." Open and the value should be shown on the left end of the resistor.

Note: There's a way to make our resistor value closer to 10k. We do that by solving for the actual sheet resistance in our simulator. We plug the R we got along with our dimensions and backsolve for the sheet resistance. Then we can re-adjust the length by using that sheet resistance, our desired resistance (10k), and the width. Then to make it conform to our standards, round it to make sure it is divisible by 3.6 micro.

3) Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked

I created a layout view from my voltage divider schematic from Lab 2, and began utilizing the 10k n-well resistor that I just drafted. I made sure to keep them 5.4 micro meters apart to conform by the DRC rules. Then I connected and arranged them in a way that mimicked my voltage divider schematic along with the pins and labels. Then I ran my DRC test, created an extracted view, and did my LVS.

Note: To make sure that each resistor is aligned at vertically, make sure each one is centered at x=0.

Now we are ready to create our 10-bit DAC, by instantiating and stacking 10 of them, labelling appropriately, running DRC, extracting, and doing another LVS.
Note: This will all take place in a new layout cell under My_10-bit_DAC cell.

4) All input and output Pins should be on metal 1

Make sure that each output and input pins are on metal 1 by clicking metal 1 drw before creating the pins.

5) DRC and LVS, with the extracted layout, your design (show the results in your lab report)

Below is the 10-bit DAC constructed with my 10k n-well voltage divider and suitably labelled to much my 10 bit-DAC schematic. I DRC'd, extracted, and LVS'd.

File Back-up Proof

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