Lab 7 - ECE 421L 

Authored by Gabriel Gabonia,

Email: gabonia@unlv.nevada.edu

November 2, 2020 

Lab description:

• Creating and drafting wide wire schematics and arrayed symbols.
• Siming arrayed symbols and laying out a wide full adder

• Back-up all of your work from the lab and the course.
• Go through Tutorial 5 seen here.

Lab:

 
Experiment 1: 4 Bit Word Inverter
 
For the first part of this lab we will be creating a 4 bit word inverter. We will be creating an inverter and then making the inverter 4 bits wide for both the input and output. We will first start with a creating a schematic using 6u/0.6u NMOS and PMOS devices.
 

Figure 1 - Inverter CMOS schematic with 6u/6u
 
After creating the inverter schematic we will create a symbol for this schematic. This symbol and schematic are 1 bit for now.
 

Figure 2 - Inverter CMOS 1-Bit Symbol
 
After creating the 1 bit symbol and schematic we will now create another schematic using the 1 bit inverter to widen it and create a 4 bit inverter.
 

Figure 3 - 4-Bit Inverter Schematic
 
After creating the 4 bit inverter schematic we will use this to create the 4 bit symbol.
 

Figure 4 - 4-Bit Inverter Symbol
 
Now that the symbol is created we can use this symbol and test the inverter in a sim. For this lab it wants to test different capacitance loads at different output bits. The loads for the 4 bits will be a 100fF, 500fF, and 1pF capacitor with one bit having no load.
 

Figure 5 - 4-Bit Word Sim
 

Figure 6 - 4-Bit Word Sim Graph
 
We can see based on the graph that as the capacitance increases for the load, the rising and falling times for the output decreases.
 
Experiment 2: Creating 8-Bit Schematics, Symbols and Sims for NAND, NOR, AND, INVERTER and OR Gates

For the next experiment we will be creating different 8-Bit Gates. We will start with the 8-bit inverter. Using the same process as experiment 1, we will use the 1-bit inverter and create a schematic for an 8-bit inverter using wide buses.
 

Figure 7 - 8-Bit Inverter Schematic
 
Using the schematic we will create a symbol and use that symbol in a sim to test the inputs and outputs of an inverter.
 

Figure 8 - 8-Bit Inverter Symbol
 

Figure 9 - 8-Bit Inverter Sim
 
The inverter in the sim gets the same input for all of the 8 bits and the output for all 8 bits should be the same.
 

Figure 10 - 8-Bit Inverter Sim Graph
 
We can see in the sim that the 8-bit inputs and outputs match that of an inverter.

Inverter Truth Table

The next gate we will be working on is the 8-Bit NAND gate. For this NAND gate we will be using the 1-bit NAND gate from the previous labs since it is already the correct sizing for this lab. We will create the 8-Bit NAND gate schematic and symbol.
 

Figure 11 - 8-Bit NAND Gate Schematic
 

Figure 12 - 8-Bit NAND Gate Symbol
 
Using the 8-Bit NAND symbol we will sim the gate and put varying inputs for the two different ports and test the busses on the output port. The two inputs have varying periods.
 

Figure 13 - 8-Bit NAND Gate Sim
 

Figure 14 - 8-Bit NAND Gate Sim Graph
 
The NAND Gate input and outputs match the truth table.
 
NAND Gate Truth Table

The next gate we will be making is the 8-Bit AND Gate. We will first need to create the schematic and symbol for a 1-Bit AND Gate. We can do this by connecting the NAND Gate with an inverter.
 

Figure 15 - AND Gate Schematic
 

Figure 16 - AND Gate Symbol
 
We will now use this symbol to create the 8-Bit AND schematic and symbol using wide buses.
 

Figure 17 - 8-Bit AND Gate Schematic
 

Figure 18 - 8-Bit AND Gate Symbol
 
Now we can sim the gate and compare it with the truth table.
 

Figure 19 - 8-Bit AND Gate Sim
 

Figure 20 - 8-Bit AND Gate Sim Graph
 
We can see that the graph of the AND gate matches the truth table.
 
AND Gate Truth Table

 
The next gate we will be working on is the 8-Bit NOR Gate. For this gate we will need to first create the 1-Bit Schematic and symbol using the appropriate mosfest sizes.
 

Figure 21 - NOR Gate Schematic
 
Now we can create the 8-Bit version of the NOR Gate both its schematic and symbol.
 

Figure 22 - 8-Bit NOR Gate Schematic
 

Figure 23 - 8-Bit NOR Gate Symbol
  
Using the 8-Bit NOR Gate Symbol we can sim and test it. We will again compare it with a truth table.
 

Figure 24 - 8-Bit NOR Gate Sim
 

Figure 25 - 8-Bit NOR Gate Graph
 
We can see that the graph of the NOR and truth table match.
 
NOR Gate Truth Table

 
The next gate and final gate is the 8-Bit OR Gate. We need to first create the 1-bit OR gate schematic and symbol. We can do this by using the NOR gate we created and connect it to an inverter.
 

Figure 26 - OR Gate Schematic
 

Figure 27 - OR Gate Symbol
 
Now that the 1-Bit OR Gate is created we can make the 8-Bit OR Gate schematic and symbol.
 

Figure 28 - 8-Bit OR Gate Schematic
 

Figure 29 - 8-Bit OR Gate Symbol
 
We can now sim the 8-Bit OR Gate and then compare the results to a truth table.
 

Figure 30 - 8-Bit OR Gate Sim
 

Figure 31 - 8-Bit OR Gate Sim Graph
 
We can see that the graph and the truth table match.
 
OR Gate Truth Table

 
Experiment 3: Schematic and Symbol for 8-Bit MUX and DEMUX
 
For this next experiment we have to make an 8-bit MUX and DEMUX. We have to first create the 1-Bit versions of the MUX and DEMUX, both the schematics and symbols. We will start with the MUX.
 

Figure 32 - MUX Schematic
 

Figure 33 - MUX Symbol
 
Now that MUX is finished we can create the DEMUX using the same schematic except reversing it since the MUX and DEMUX work both ways.
 

Figure 34 -  DEMUX Schematic
 

Figure 35 - DEMUX Symbol
 
Now that both the MUX and DEMUX 1-Bit schematics and symbols are made we can use these to create the 8-Bit schematics and Symbols. We will start with the MUX.
 

Figure 36 - 8-Bit MUX Schematic
 

Figure 37 - 8-Bit MUX Symbol
 
We can now Sim the 8-Bit Mux and compare it to a MUX Truth Table.
 

Figure 38 - 8-Bit MUX Sim
 

Figure 39 - 8-Bit MUX Sim Graph
 
Comparing it to a truth table we can see that the graph matches. If S=1 it will choose A and if S=0 it will choose B.
 
MUX Truth Table

Now the next thing to create is the 8-Bit DEMUX schematic and symbol.
 

Figure 40 - 8-Bit DEMUX Schematic
 

Figure 41 - 8-Bit DEMUX Symbol
 
Now that the 8-Bit DEMUX schematic and symbol are created we can sim and compare to a truth table.
 

Figure 42 - 8-Bit DEMUX Sim
 

Figure 43 - 8-Bit DEMUX Graph
 
We can see that the S determines where the input Z will go. If S=1 then Z will go to outa and if S=0 then Z will go to outb.
 
DEMUX Truth Table

 
Experiment 4: 8-Bit Full Adder
 
For the next experiment we will be making an 8-bit full adder. We first need to make the 1-bit full adder schematic and layout. We will base the full adder design from fig 12.20 in the book. We will use the sizing of 6u/0.6u for the NMOS and PMOS. After creating the schematic we will create a symbol of the full adder as well.
 

Figure 44 - Full Adder Part 1
 

Figure 45 - Full Adder Part 2
 

Figure 46 - Full Adder Symbol
 
After Creating the Symbol we will need to layout the schematic. Since the schematic was big, the layout was separated into two parts to make it easier. Simply laying out part 1 and part 2 separtately, testing DRC and LVS saves more time than laying out all together and helps catch errors faster. After both were successful, you can just put them together in the final layout.
 

Figure 47 - Complete Full Adder Layout
 

Figure 48 - Full Adder DRC
 

Figure 49 - Full Adder LVS
 
We can now implement the full adder we created into an 8 bit full adder by first creating the schematic then the symbol. We will create a different schematic for laying out, our first 8-bit full adder creation will be for siming and testing.
 

Figure 50 - 8-Bit Full Adder
 

Figure 51 - 8-Bit Full Adder Symbol
 
After creating the schematic and symbol for our first 8-bit full adder we will use this one in our sim test.
 

Figure 52 - 8-Bit Full Adder Sim
 

Figure 53 - 8-Bit Full Adder Sim Graph
 
We can see that our 8-Bit full adder should be working correctly using results from a truth table.
 
Full Adder Truth Table

Seeing that everything is working correctly, we can start on the layout of the Full Adder. For this full adder we will use a different 8- Bit Schematic as the carry in and carryout need to be connected together.
 

Figure 54 - 8-Bit Full Adder Schematic for Layout
 
The layout will need to have all of the input pins <7:0> from a and b. The layout will also need to have all of the output pins labeled <7:0> from s. The first full adder will have the input cin. The following full adders after the first will have the cout connected to the cin of the next full adder. The final full adder at the end will have the output pin cout<7>.
 

Figure 55 - 8-Bit Full Adder Layout, Last Full Adder View
 

Figure 56 - 8-Bit Full Adder Layout Overall View
 

Figure 57 - 8-Bit Full Adder DRC
 

Figure 58 - 8-Bit Full Adder LVS
 

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