The ethernet signal go though a long wire will lose the intergrity of the signal. The voltage will drop though the long ethernet cable transistion. We are building a signal buffer for the ethernet cable. So we don't need to worried about the length of the cable is affecting the intergraity of the signal.
Schematic:
1. NMOS self bias circuit.
NMOS self bias circuit.
NMOS signal buffer circuit with two inverters, the reason we put inverter in the circuit is to create a nice and shape waveform. instead of a soft waveform. Here is the schematic of the circuit:
Symbol:
We are putting two buffer together let it do the job that together and here is the circuit for it.
And here is the symbol of it.
Simulation:
So we build the simulation circuit to verify the result of the signal buffer that we build. Here is the circuit. By changing the input signal frequncy we can test the frequncy response for the signal buffer.
And we are runing simulation of this circuit under 100mhz so here is the simulation result.
And we change the frequncy to 200 mhz.
Final we change the frequncy to 250 mhz. And the result looks good, the output signal still hold their eages.
We are doing the temperature analysis and we are sweep from 0 C to 100 C. Here is the grapgh of it.
We can see if with the temperature increase, we are having a higher delay then the low temperature. It should be due to the captiance change in the MOSOFT cause that.
Also we test the effect to the circuit when we changing the vdd level. Here is the result when we sweep it from 5v to 2.5v.
VDD = 5V
VDD = 4V
VDD = 3.7V
VDD = 3.3V
VDD = 3.1V
VDD = 3V
VDD = 2.7V
VDD = 2.5V
From the simulation result we find out when vdd drop it to around 3.1V it started losing edges and when the VDD drop under 3V the output signal went under 3V. That is when the signal competely lost. When the VDD drop it to 2.5V, the signal competely went drak, there will be no logic output.
Part 2:
Here is the nmos-bias signal buffer's layout, DRC and LVS.
Here is the pmos-bias buffer layout, DRC and LVS.
Here is the full buffer layout, DRC and LVS.
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