Lab 8 - ECE 421L 

Authored by Tian Chen

12/1/2020 

  

Prelab:

We are build a test chip this time, we are using all the previous layout that we design before to make a test chip using the pieces in previous lab.

We build the pad first, we use a 75um metal 3 square around a 63 um glass square. Here is the layout and schematic.

And we are building 10 X 10 pad frame, and here is the schematic and layout for the pad frame.

Then we are build the schematic for the test chip.

Afterwards we are doing the DRC and LVS for the layout, here is it.

Lab project:

The lab project is almost the same with prelab, but with more component. Here is the pin table for our chip

PinDeviceDescrription
1Ring oscillatorOutput
2NORA
3NORB
4NOROutput
5NoneNone
6NoneNone
7NMOSDrian
8NMOSGate
9NMOSSource
10NoneNone
11PMOSSource
12PMOSGate
13PMOSDrian
14PMOSBase
15InverterInput
16InverterOutput
17Voltage dividerInput
18Voltage dividerOutput
19NoneNone
20VDDVDD
21NANDA
22NANDB
23NANDOutput
24NoneNone
25NoneNone
26NoneNone
2725k n-well resistorinput/output
2825k n-well resistorinput/output
29NoneNone
30Full adderA
31Full adderB
32Full adderCarry in
33Full adderSum
34Full adderCarry out
35NoneNone
36NoneNone
37NoneNone
38NoneNone
39NoneNone
40GNDGND


Base on the pin map that we have, we layout the pin map and DRC and LVS the layout.


 

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