Lab 6 - ECE 421L 

Authored by Tian Chen,

email: chent5@unlv.nevada.edu

10/21/2020

  

Prelab:

We are going though the tutorial 4 and we are building a NAND gate with the  PMOS and NMOS. And here is the schematic and the layout.

And here is the symbol that we made out of this schmatic

 Here is the layout that we made for the NAND gate and the DRC of the NAND gate


Here is the extracted view of the NAND gate layout with LVS result

Afterward we are using the symbol that we build before to build a simulation circuit to test if the NAND gate is working. Here is the circuit and the simulation result.

Lab expriment:

    Experimennt 1: NAND gate 

        We did the NAND gate layout and the simulation in the prelab, please check that.

    Experiment 2 : XOR gate

        We are using PMOS and NMOS to build a XOR gate. Here is the schematic 

        

        Base on that schematic we are using that to make the symbol 

        Then we are using the symbol to build a testing circuit to perform the simulation of the XOR gate, here is the circuit and the simulation result

        We got the simulation result that we want, the glitch is happening everytime when the we change the state, that happened is because the response time of the mosfet that we are             using. Practically the glitch will always be there. Here is the truth table of theXOR.

ABA XOR B
000
011
101
110
        So we can see the simulation result match the truth table. Our circuit is verified.

        From here on we started to layout the XOR gate here is the layout and DRC for the layout

        Here is the extracted view of the XOR gate and the LVS of the XOR gate


        So we finished the experiment2 XOR gate layout

    Experiment 3: Full adder

        We are using the XOR gate and NAND gate to make the full adder. Here is the schematic of the circuit.

        Base on the schematic we generate the symbol of the full adder.

   

   

        We are using this symbol to generate a simulation circuit and here is the circuit and the simulation result

         the truth table for the full adder is

abcinscout
00000
00110
01010
01101
10010
10101
11001
11111
        the simulation result match the truth table. The symbol is verified

        Then we are going to layout the full adder and here is the layout and DRC




        Then we extracted the layout and here is extracted view and LVS

   

Here is all the lab about lab 6.

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