Lab 5 - ECE 421L
Authored
by Tian Chen,
10/07/2020
chent5@unlv.nevada.edu
Pre-lab:
We are doing the pre-lab to finish the tutorial 3, So we
follow the step create a inverter circuit using, last lab's PMOS and
NMOS. And here is the circuit that we create.
Using the schematic of the circuit we create the symbol base on that using (create / Cell view / From cell view)
From that we create the layout of the simple invertor.
And then we extract the layout into a extracted form.
then we are using the symbol of the inverter to make circuit and generate the simulation result base on that.
Here is the simulation result without the VDD.
This
is not the result we are looking for, because the invertor is not power
on. We are going to add the globa valve to make the result that we want.
So we finished the pre-lab, that is the result we are looking for.
Lab :
Experiment 1:
We are going to make a 48u/24u invertor using the multiplier, so here is the schematic.
Then we creat the symbol base on this schematic.
And then we create the layout of the 48u/24u invertor, And here is the DRC of the layout.
Base on the layout we extact the layout, and perform LVS on it here is the screen shot.
We finished the layout of the invertor and we can perform the experiment 2 after this.
Experiment 2:
We are using the symbol that we creat for the invertor to perform simulation, here is the schematic that we build.
After
we finish build the circuit we launch the ADE to perform the
simulation. Here is the simulation result when we change the
capacitance from 100fF to 100pf.
After
all the simulation we can find out the with the size of the capacitor
increase, the response time for the signal started to increase. It will
get a lot smaller gains. But it is trying to smooth out the signals.
Experiment 3:
We are using Ultrasim for this experiment and here is the simulation result.
I backed up all of my file into my google drive.
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