Lab 7 - ECE 421L
I ran the LVS and it failed, as expected. I modified the schematic with a pin and a new wire label and it LVSed properly:
I then created a symbol from the schematic and used it in a simulation circuit:
I then created a schematic to simulate the circuit, with the following results:
As you can see, the top output is out<0>, which is not connected to any capacitor and it has the lowest delay time. Out<1> is tied to a large 1pF capacitor, and so it has a very large delay, hence why its curve is is very smooth. Out<3> is connected to a very small 100fF capacitor, so it is more similar to out<0>. Therefore, the simulation results support the time delay equations (since the time delay is directly proportional to capacitance).
For the next portion of the lab, I made an 8-bit IO NAND, NOR, AND, inverter, and OR gates.
The NAND and it's simulations are shown below (the inputs are on the bottom). The simulation results accurately represent the truth table:
NOR gate and simulation (inputs are on the bottom). The results are accurate to the truth table:
AND gate and simulations:
Inverter and sims:
OR gate:
The next task of the lab was to simulate the provided MUX circuit to demonstrate its multiplexing and demultiplexing capabilities. The simulation schematics and results are shown below.
The first two screenshots show the MUXing schematic and results. In the simulation results, the two selection bits are up top and the output is on the bottom. As you can see, when the selection bits change, the mux switches to the higher frequency output. The two screenshots after that are meant to demonstrate the de-MUXing capabilities. In the simulation screenshot on the bottom, the mux takes the signal inputted to Z and outputs it to A or B depending on the state of the selection bits:
For the next portion of the lab, I made an 8-bit wide version of the MUX with an inverter (to half the number of selection bits) and then simulated that version. In the simulation results, the two top signals are the inputs, and the third signal is the selection bit. As you can see, the output bits switch between the signals when the selection bit changes.
Finally, for the last portion of the lab, I made the schematic for an full adder, simulated it to prove its operation, and created a layout of the full adder. I DRCed and LVSed the layout and then created and simulated an 8 bit version and went to bed.
The following three images are the full adder schematic's top half, bottom half, and the full image.
Then I made a symbol and a simulation circuit. As you can see in the simulation results, the carry out and sum bits match the truth table:
Finally, it was time for the 8 bit simulation. In order for it to be a true 8 bit adder, the carry-in bit has to be taken from the previous adder's carry-out bit. This was achieved below by using the command "Cin,Cout<1:7>". I made a very ugly symbol from the 8 bit adder schematic, which is shown in the simulation schematic. The simulation schematic is fairly simple; voltage sources are set to 5 to represent 1 and set to 0 to reperesent 0. The A input is accepting 01010110, which is 86 in binary. B accepts 01011101, which is 93. The output is 10110011 (the MSB is the output Sum<8>, so it is read from top to bottom (net07 is the carry-out bit)). This is 179 in binary which is the correct answer.
