Lab 7 - EE 421L 

Authored by Shaquille Regis

Email: regis@unlv.nevada.edu

November 6, 2019

Lab description:

Using busses, we can create arrays of devices while maintaining a clean schematic area. We will expand on the logic

gates made in previous labs by using busses and simulating these expanded gates.

Pre-lab Work:

Go through Tutorial 5 as seen here. Tutorial 5 covers the design, simulation and layout of a ring oscillator as well as

how to efficiently make arrays of devices by using buses.

Lab Procedure:

1) Create a 4-bit inverter using busses.

Typically, an array of devices (in this case inverters) can be drawn in schematic as shown below.

An equivalent, more concise schematic can be drawn by instantiating the one inverter by adding the array indicator next

to the instance name when viewing the instance properties ('Q'). The corresponding input and output pins should be labeled

to indicate the width of the instance array (<3:0> for a 4-bit wide device).

Symbol View

Simulation Schematic

Simulation Graph

2) Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, OR and inverter gates.

8-bit NAND Gate

Schematic

Symbol

Simulation Schematic

Simulation Graph

8-bit NOR Gate

Schematic

Symbol

Simulation Schematic

Simulation Graph

8-bit AND Gate

Schematic

Symbol

Simulation Schematic

Simulation Graph

8-bit OR Gate

Schematic

Symbol

Simulation Schematic

Simulation Graph

8-bit Inverter

Schematic

Symbol

Simulation Schematic

Simulation Graph

3) Create a 2-to-1 MUX/DEMUX

The multiplexer/de-multiplexer operates by turning on a specific TG at a time. For example, if S is high, the output Z is B. If Si is high, or S is low, the output Z is A.

Schematic

Symbol

Simulation Schematic

Simulation Graph

4) Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.

Schematic

Symbol

Simulation Schematic

Simulation Graph

5) Create an 8-bit Full Adder

Using the schematic previously created in lab 6, we can expand its size to accomodate the desired bit width using busses.

Schematic

Symbol

Simulation Schematic

Simulation Graph

Full Layout

Close-up of the first full adder (bit 0). Note that cout of the first full adder is connected cin of the second full adder via metal3 connection. Each subsequent cout/cin connection is required at each full adder.

Close-up view of the last full adder (bit 7).

Extracted View

DRC

LVS

As always, remember to backup all lab materials to zip folders and email.

End of Report

Return to Shaq's Labs