Lab 6 - EE 421L 

Authored by Shaquille Regis

Email: regis@unlv.nevada.edu

October 23, 2019

Lab description:

Using NMOS and PMOS transistors, we will design, layout and simulate CMOS NAND and XOR gates

as well as design, layout and simulate a full-adder using the previously mentioned gates.

Pre-lab Work:

1) Backup all of your course work from the lab and the course.

2) Go through Tutorial 4 as seen here. Tutorial 4 goes over the design, layout and simulation of a NAND gate.

    The schematic for a NAND gate comprises two NMOS transistors in series and two PMOS transistors in

    parallel. The same schematic is used for the main lab procedure.

Symbol View

Layout                                                                      Extracted

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Lab Work:

1) Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS).

    All cells are to be named using your initials and the current year/semester (ex. nand2_sr_f19). Symbol views must include your initials.

- NAND Gate

Symbol View

Using the NAND gate created from Tutorial 4 as a template, add a rectangle n-well layer around the PMOS transistor to create a unit cell that

can be lined up and layed out with other components and vdd!/gnd! nets. The n-well layer has a length of 14.4 micron and width of 12 micron

to line up with an n-tap with 7 contacts for vdd!.

Layout                                                                 Extracted

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-XOR Gate

The XOR gate comprises two inverters that accept inputs A and B to be inverted: Ai and Bi, respectively.

A, B, Ai and Bi are then used as inputs for the transistor array next to the two inverters. This transistor

array comprises two sets of two PMOS transistors connected in series and two sets of NMOS transistors

connected in series. The sets of PMOS are connected in parallel at the drain/source connections between

the two series PMOS and at the drain/drain connection between the sets of PMOS and sets of NMOS.

Schematic

Symbol View

Layout

As mentioned in the layout for the NAND gate, unit cells for the transtors were created to ensure easy alignment

of component cells in the layout.

Extracted

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2) Simulation of gates

- Create a new schematic that contains instances of the NAND and XOR gates and the inverter created previously

  created in lab 5. All gates will be connected to two pulse sources that simulate 2-bit incrementation from 00 to 11.

Schematic

Simulation

Note that the output of the XOR gate (AxorB) briefly goes to 0V near 200ns when A = 5V and B = 0V, or in binary A = 1 and B = 0.

This is due to the overlap in the rising edge of A and falling edge of B causing a false output of binary 0 during the input transistion.

Below are the truth tables for the NAND gate and XOR gate for verification

NAND

XOR

3) Using the gates created above, draft the schematic, layout and simulate a Full-Adder. A full-adder is a logical circuit that performs

    addition of two 1-bit signals and a carry-in bit. The output is a 1-bit answer with a 1-bit carry if required.

Schematic

Symbol

Layout

Extracted

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Simulation Schematic

Simulation Graph

Shown below is the truth table for the full-adder for verification.

As always, remember to backup all lab materials to zip folders and email.

End of Report

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