Lab 8 - ECE 421L
Authored
by Geovanni Portillo, Yared Abraha
Emails: portig1@unlv.nevada.edu and abrahy2@unlv.nevada.edu respectively.
Last edited Dec 2nd, 2019
Generating a test chip layout for submission to MOSIS for fabrication
Pre-lab tasks
- Back-up all of your work from the lab and the course.
- Go through Cadence Tutorial 6 seen here.
- Should end up with creating pad, padframe and a chip cell as shown below.
- Read through the lab in its entirety before starting to work on it
| Schematic | Layout |
| Pad |  |  |
| Padframe |  |  |
| Chip |
| Schematic |  |
| Layout |  |
| Extracted |  |
| DRC |  |
| LVS |  |
Lab 8:
Guidelines
- Each test circuit should have its own power but ground should be shared between the circuits.
- Ground should be pin 20.
- Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable.
Your chip should include the following test structures:
- One, or more if possible, course projects
- A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
- NAND and NOR gates using 6/0.6 NMOSs and PMOSs
- An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
- Transistors,
both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each
device are connected to bond pads (7 pads + common gnd pad)
- Note
that only one pad is needed for the common gnd pad. This pad is used to
ground the p-substrate and provide ground to each test circuit
- Using
the 25k resistor laid out below and a 10k resistor implement a voltage
divider (need only 1 more pad above the ones used for the 25k
resistor)
- A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)
- Whatever else you would like to fabricate to use the remaining pins on the chip
The design directory for Chip3_f19 can be downloaded here.
| Chip3_f19 |
| Schematic | Layout |
 |  |
| DRC | LVS |
 |  |
The components and their connections are listed below. Ground is shared at pin<20> whenever ground is needed.
| Summary of Chip Operation |
 |  |
For the NMOS, the drain is connected to pin<17>, the gate to pin<18> and the source to pin<19>.
| NMOS |
| Schematic | Symbol |
 |  |
| Layout | Pins |
 |  |
For
the PMOS, the body is connected to pin<23>, the source to
pin<24>, the drain to pin<25> and the gate to pin<26>.
| PMOS |
| Schematic | Symbol |
 |  |
| Layout | Pins |
 |  |
For the voltage divider, the input is connected to pin<21> and the output is connected to pin<22>. | Voltage Divider |
| Schematic | Symbol |
 |  |
| Layout | Pins |
 |  |
For
the inverter, the VDD is connected to pin<14>, the input is
connected to pin<15> and the output to pin<16>.
| Inverter 12u/6u (Minimum Length) |
| Schematic | Symbol |
 |  |
| Layout | Pin |
 |  |
For the NAND gate, VDD is connected to pin<6>, A to pin<7>, B to pin<8> and AnandB to pin<9>.
| NAND |
| Schematic | Symbol |
 |  |
| Layout | Pins |
 |  |
For the NOR gate, VDD is connected to pin<10>, A to pin<11>, B to pin<12> and AnorB to pin<13>.
| NOR |
| Schematic | Symbol |
 |  |
| Layout | Pins |
 |  |
For the ring oscillator with a buffer, both VDDs are connected together at pin<5> and the output to pin<6>.
| 31-Stage Ring Oscillator |
| Schematic | Symbol |
 |  |
| Layout |
 |
| Buffer |
| Schematic | Symbol |
 |  |
| Layout |
 |
| Pins |
 |
For
the BSPS, VDD is connected to pin<3>, Vin to pin<1> and
Vout to pin<2>. Vin is connected to the drain of the switching
NMOS of the BSPS and Vout is used for feedback of the off-chip circuit.
Testing of this chip requires supplying a range of 3.75V - 5.25V to pin<3>, the negative terminal of an inductor and Schottky diode to pin<1> and connecting to output of the off-chip circuit back to pin<2>.
BSPS can be simulatued using the BSPS cell in the design directory.| Boost Switching Power Supply (BSPS) |
| Schematic | Symbol |
 |  |
| Layout | Pins |
 |  |
The design directory for Chip3_f19 can be downloaded here.
This concludes the report for Lab 8.
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