Lab 5 – Design, Layout, and SIM of CMOS Inverter
EE 421L - Fall 2019
Authored by Lizz Heider
heider@unlv.nevada.edu
Submission
Date: 9/24/2019
QUICK
SUMMARY ON INVERTERS
·
An inverter… INVERTS meaning:
š PMOS connected to NMOS with Input A and Output Ai
š High Input – Low Output & Low Input – High
Output
š Current is only flowing when the voltage is
changing.
Here’s a
summary
In tutorial 3 we draft the schematic, symbol, and layout of a CMOS
Inverter.
Then we also simulate the DC behavior of the inverter.
Part 1 + 2: Create a schematic and layout out of a CMOS inverter
Part 3 – Extract Layout (no photo) and LVS check
Part 4 – A symbol was created for this Inverter, then used for
simulation
No output because there is no Vdd source - add Vdd source and setup in ADE Setup -Stimuli
Results in the following output:
(above) DC Characteristics of Inverter. Low input, High Output.
LAB BREAKDOWN
(A)
Draft schematics, layouts, and symbols for two inverters having
sizes of
1.
12u/6u (width of PMOS / width of NMOS with both devices having
minimum lengths of 0.6u)
2.
48u/24u where the devices use a multiplier, M=4 (set along with
the width and length of the MOSFET)
(B)
Using SPICE simulate the operation of both of your inverters
showing each driving a 100 fF, 1pF, 10 pF, and 100 pF
capacitive load
12u/6u
INVERTER 48u/24u
INVERTER M = 4
1pF
100pF
(C)
SPICE Simulations
(ULTRASIM SIMULUATIONS)
Ultrasim and Spice
output the same results.
Observe that with larger MOSFETs (L/W) we see faster fall times and higher
gains.
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