Lab

Lab 4 – IV Characteristics & Layout

EE 421L Fall 2019
Authored by Lizz Heider

è heider@unlv.nevada.edu ß

Submission Date: 9/24/2019

PRELAB

· Back that lab(s) up ✔

· Tutorial 2 ✔

My labs are backed up onto my personal computer. Yay.

Here’s a summary of Tutorial 2:

ð In this tutorial we’ll lay out and simulate the operation of NMOS and PMOS transistors using the C5 process.

· Created Schematic, Symbol, Layout and Simulation of NMOS Transistor

· Same as above with PMOS

BELOW:Symbols, everything else in the tutorial is used in the lab.

LAB PROCEDURE

Generate 4 schematics and simulations.

(1) A schematic for simulating ID v. VDS of an NMOS Device for VGS varying from 0 to 5V in 1 V steps while VDS varies from 0 to 5V in 1mV steps.

(LEFT) schematic used to simulate ID v. VDS of an NMOS device.

(RIGHT) Simulation of ID V. VDS

Note that (for above figures):

- VGS varies from 0 to 5V in 1V steps

- VDS varies from 0 to 5V in 1mV steps

(2) A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.

(3) A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.

(4) A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.

(B) Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small).