Lab 7 – EE421L

Using buses and arrays in the design of word inverters, muxes, and high-speed adders.

heider@unlv.nevada.edu

Lizz Heider

Submitted November 5, 2019

Pre-Lab

The pre-lab was TUT5

Design, Layout, and Simulation of a Ring Oscillator

LAB 7

I) CREATING A 4-BIT INVERTER

Begin with creating a schematic for the 4-bit inverter and the symbol:

We simulate with the capacitive loads instructed.
Observe: the larger the load capacitance, the longer the delay will extend.

II) 8-BIT GATES

8-BIT NAND GATE

8-BIT NOR GATE

8-BIT AND GATE

8-BIT OR GATE

III) 2-to-1 MUX/DEMUX

Observing the simulation for the 2-1 MUX/DEMUX:
When S is high, output Z follows input A
When S is low, the output Z follows input B

DEMUX, Observe:
When S is high, the input signal Y propagates through to C only
When S is low, the input signal Y propagates through D only

IV) 8-bit wide word 2-to-1 MUX/DEMUX schematic and symbol

ð When S is high, all 8-bits of output Z follow input signal A

ð When S is low, all 8-bits of output Z follow input signal B

Our select is HIGH, therefore, word B will pass. B<7:0> = 0011 0011

V) 8-Bit Full Adder

For A,         A<7:0> =     1010 1010,

+                 B<7:0> =      0011 0011.

C<7:0> = A + B        =  0 1101 1101

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8-Bit Full Adder Layout + Extracted View + LVS Verification

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