Lab 6 - ECE 421L
Design, layout, and
simulation of a CMOS NAND gate, XOR gate, and Full-Adder
heider@unlv.nevada.edu
Prelab –
Design, Layout, Simulation – 2-input NAND Gate – Layout and Extracted View
We do this using a 6u/0.6u MOSFETs (both NMOS and
PMOS)
A DRC and LVS
was also ran for the NAND gate below:
LAB 6
(1)
Draft the schematics of a 2-input NAND gate, and a 2-input XOR
gate using 6u/0.6u MOSFETS
Below is the
symbols for NAND and XOR, respectfully
(3) Layouts of
NAND gate and XOR gate
- Before
continuing I made a standard cell frame, taller than what we usually use (for
future use), as instructed.
standard cell frame -
NAND Gate Layout - Extracted
NAND Layout
XOR Gate Layout - Extracted XOR Layout
(4) Simulation of Gates Inverter, XOR, NAND,
(5) FULL ADDER
(Below) Full
Adder Schematic
(Below) Full
Adder Layout, Extracted Layout
(Below) Full
Adder Schematic for Simulation, then Transient Simulation
** GLITCHES **
Glitches, that we can see
in our output, are caused by the brief rise and fall times of the input
signals.
When there is a time period where the pulse is rising or falling, & the
MOSFETs are neither on, nor off, for that instant.
The glitches are smaller when the rise/fall times are decreased.
An ideal rise/fall time
(zero, meaning ideal) would result in no glitch. (So, we’ll always have
glitches)
(Below) Naming
my cells LH_F19 (I almost forgot about this so some I renamed them at the end)
