Lab 6 - EE 421L
The pre-lab consisted with going through Tutorial 4 which we learn how to design, lay out and simulate the operation of a NAND gate (same NAND gate will be used for LAB 6 but with different size) but instead of using NMOS and PMOS cells we will be using our NMOS device using rectangles. This started by copying Tutorial 3 onto a new library called Tutorial 4 and making sure that we upade the instances when we copy it. For this pre-lab I created a schematic, symbol, and layout for my NAND gate and I simulated my NAND gate to make sure that it fulfills its function.
NAND Schematic
NAND Symbol
NAND Gate Simulation Schematic
NAND Gate Simulation Result
NAND Layout
Extracted Layout
DRC and LVS Result
For this lab, I began by creating a 2-input NAND gate and a 2input XOR gate using 6u/0.6y MOSFETs (both NMOS and PMOS). I copied my Tutorial 4 library to a new library called Lab_6 and used the NAND gate (but changed the size of the MOSFETs used to 6u and 0.6u in the layout) to start this laboratory. Below are the schematic, layout and symbol for my 2-input NAND gate.
Part 1: NAND Gate Schematic,Symbol and Layout
NAND Schematic
NAND Symbol
NAND Layout
DRC and LVS Result of Nand Layout
Part 2: XOR Schematic, Symbol, and Layout
XOR Symbol
XOR Layout
XOR Gate DRC and LVS
Part 3: Behavior Gate Symbols and Simulation
The behavior gates consists of an inverter, a nand gate and a xor gate. For all of these gates, they are all created already (Nand and Xor gate created previously as seen and Inverter created from previous lab).
Schematic
Simulation
Part 4: Full Adder Schematic, Symbol, Layout, and Simulation
Full Adder Schematic
Full Adder Symbol
Full Adder Layout
Full Adder DRC and LVS
Full Adder Simulation
Simulation Schematic
Simulation Result
-> On the simulation, the glitches are caused by transitioning of A and B at the same time. Adding inverters to the schematic will help minimize this error in our output.
Files that are used in this lab: Lab_6_files