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Lab 6 - EE 421L - Fall 2019
Design, Layout, and Simulation of a CMOS NAND Gate, XOR Gate, and Full-Adder
Rebelmail: buenj1@unlv.nevada.edu
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Schematic and Layout of a 2-input NAND Gate
In tutorial 4, we were introduced to the schematic, symbol, sim-schematic, and layout of a 2-input NAND gate. For this lab, the schematic, symbol, and layout of the NAND gate will be re-used, but with small changes.
I have edited the layout of the NAND gate and included more contacts for both the vdd! and gnd! pins. The reason why I did that is because when instantiating the NAND gate for the full adder layout, connections to
other elements in the layout will be cleaner and have enough space in between. I also changed the size of the PMOS transistor to 6u/0.6u in the schematic cell as we were told to have all MOSFETs be of that size.
Schematic Symbol (with my initials in the middle) Layout
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Extracted
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-> DRC and LVS of 2-input NAND Gate
DRC LVS
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Schematic and Layout of a 2-input XOR Gate
The 2-input XOR gate is a little bit more complicated to layout. The schematic cell of the XOR gate includes 2 instantiations of the inverter. Then, the inputs and outputs of the inverters are then mapped to 4 other PMOS and NMOS devices resulting in the schematic shown below. For the layout, I grouped together the 4 PMOS and NMOS in the middle and the two inverters on the outer side. The two inverters on the outer side of the layout are left alone and the 4 PMOS and NMOS devices are grouped using 4 fingers (m = 4).
Schematic Symbol (with my initials)
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Layout Extracted
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-> DRC and LVS of 2-input XOR Gate
DRC LVS
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Simulation of the Logical Operation of All Gates Made so Far (INVERTER, NAND, XOR)
The following images shown involve the simulation of all of the gates made so far and test their logical operations. The sim-schematic also involves the inverter gate that was constructed a while back.
The possible inputs to test are 00, 01, 10, 11 for the 2-input gates (NAND and XOR).
Sim-schematic Layout
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Notice the sudden spike on the AxorB output for the 2-input XOR gate function. The sudden spike in the above simulation is a "glitch" which is a brief time period where there is a small rise and fall time (a quick pulse) caused by sudden changes of the input signals' rise/fall times.A circuit with ideal rise and fall times would eliminate glitches in the simulation.
Truth Table for the 3 gates:
| A | B | Ai | AnandB | AxorB |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 |
Schematic, Sim-Schematic, and Layout of the Full Adder
The full adder circuit is composed of 2 instantiations of the XOR gate and 3 instantiations of the NAND gate. The truth table for the full adder is shown below with a cin input and 2 outputs: sum (s) and cout.
Full Adder Truth Table:
Schematic of Full Adder Symbol of Full Adder
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Simulation Schematic and Simulation of Full Adder
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From the sim-schematic above, 3 voltage pulses are placed on the 3 inputs of the Full Adder. For each of the pulses used for the transient analysis, I had to time them specifically so that each input signal has the proper bit sequences as shown above to cleanly demonstrate and test the functionality of the full adder.
Again, glitches are present in the simulations especially in the outputs of the full adder. (due to sudden changes in the input signals)
Full Adder Layout:
Extracted view of Full Adder:
The layout of the full adder as shown above, like the schematic, is composed of 2 instantiations of the XOR gate (in layout) and 3 instantiations of the NAND gate (in layout). I layed out the full adder in the order of 1 NAND layout on the very left, 2 XOR layouts in the middle, and the 2 remaining NAND layouts on the right. I also had routed the input and output pins on the peripheral of the overall layout in case I have to connect the full adder to other instantiated cells.
-> DRC and LVS of the Full Adder
DRC LVS
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Lab 6 Zip File: lab_6.zip