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Lab 5 - EE 421L - Fall 2019
Design, Layout, and Simulation of a CMOS Inverter
Rebelmail: buenj1@unlv.nevada.edu
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12u/6u Inverter (12u width of PMOS/6u width of NMOS, both have a length of 600n):
To make an inverter in the schematic, a PMOS and an NMOS have to be used. The source of the PMOS is connected to a VDD of 5V (logic 1) and the drain is connected to the drain of the NMOS. Following that,
the source of the NMOS will be connected to ground. The gate terminals on both transistors will be connected together forming the input of the schematic (A). The two drain terminals connected from both transistors
will represent the output of the schematic (Ai). As always, the bulk of the PMOS is connected to vdd! and the bulk of the NMOS is connected to gnd!. Schematic is shown below with its corresponding symbol.
Schematic Symbol
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Layout, Extracted view, DRC, and LVS of the 12u/6u inverter
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The schematic and layout are similar to the schematic and layout in Tutorial 3. Only changes I made to the layout were the number of rows and columns of the ntap and ptap connections. The layout DRC'ed successfully and
it LVS'ed successfully.
48u/24u Inverter (48u width of PMOS/24u width of NMOS with same length of 600n):
The schematic for this inverter will have the width of both the PMOS and NMOS multiplied by 4 resulting in the 48u/24u overall size of the inverter. The widths of both the PMOS and NMOS will not be manually changed
because the multiplier that is set equal to 4 will automatically set the widths to be 48u/24u. The length of both transistors will remain to be 600n. Schematic with its corresponding symbol shown below.
Schematic Symbol
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Layout, Extracted view, DRC, and LVS of the 48u/24u inverter
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The layout view of this inverter resulted in multiple poly layers, as well as multiple source and drain terminals which is due to the multiplier.
PART II: Simulating Both Inverters with Varying Capacitive Loads (using Spectre and Ultrasim)
Simulating the 12u/6u inverter:
The following schematic is used to simulate the inverter with a varying capactive load. The inverter symbol is instantiated in the schematic. There is also a reference voltage included in the schematic in order to operate the
inverter. The capacitor will be connected to the output of the inverter (Ai) with varying capacitance values to test and observe - 100fF, 1pF, 10pF, and 100pF.Lastly, the input of the inverter (A) will be supplied a pulse
voltage source from 0 to 5V with a rise time of 1ns and a pulse width of 10ns.
Notice, on the schematic, the capacitor value is a variable named 'capvalue' that will be used for parametric analysis. This is because I wanted to simulate each value of the capacitor in 1 simulation, showing all of the plots
in 1 graph (to reduce the work and make life a little bit easier for me).
Parametric analysis
For this analysis, I performed a decade sweep which will simulate each of the capacitance values from 100fF - 100pF
with a increments of 10pF.
Spectre simulation
The simulation by parametric analysis shows the multiple capacitance values in 1 graph.
Ultrasim Simulation of 12u/6u inverter:
Purpose of ultrasim is to simulate larger and more complicated circuits. However, ultrasim is only limited to a transient analysis. The following simulation looks almost identical to the Spectre simulation, but slightly
more precise and cleaner.
Simulating the 48u/24u inverter
The same process is done for the 48u/24u inverter. The symbol for the 48u/24u inverter is used for the schematic. Parametric analysis is also performed for all capacitance values.
Simulation Schematic
Spectre simulation
This simulation has greater fall times than the previous simulation for the 12u/6u inverter.
Ultrasim simulation for 48u/24u inverter
The ultrasim is also almost identical to it's corresponding Spectre sim but with more precise and cleaner values.
LAB ZIP FILE: lab5_jpb.zip