Lab 3 - EE 421L - Fall 2019

Authored by John Patrick Buen 

Email: buenj1@unlv.nevada.edu

9/11/2019 

Prelab:

I finished Tutorial 1 and was introduced to layout design on Cadence.

Schematic                                                                                                 Layout

->     

Final Design of DAC: lab3_DAC_finaldesign.zip

Lab 3 consists of constructing the layout design on Cadence for the DAC from the previous lab (lab 2). Following that, the design has to go through verification processes involving DRC and LVS.

To begin, I signed into MobaXterm, cd into CMOSedu, and 'virtuoso &' to get into Cadence. Afterwards, I made a new library named "lab3_DAC_finaldesign" and copied my DAC schematic and 

simulations onto the new library. To get setup with a new layout design, select a library (chose the new library that I created) and navigate as follows: File -> New -> Cellview. The following window 

should appear..

        As shown above, a small window should appear and "layout" must be selected for the type of design we are doing on the DAC. 

Following that, the layout window should appear. To begin making the resistor, the n-well layer must be chosen and layed out onto the grid.

At this point, a green rectangular shape should be layed out like shown above. That is the n-well (not yet defined as a resistor and with unknown dimensions)

The Dimensions of the N-Well and How to Determine the Length and Width

According to MOSIS: 

                                  In the C5 process, lambda = 0.30um. The minimum width of the n-well is 12 lambda or 3.6 microns (12 * 0.30 microns).

To calculate the length and width of the n-well resistor, the following resistor equation should be used: 

        The value roh/t is called the "sheet resistance." In the C5 process, sheet resistance of an n-well is roughly 800 ohms. Thickness (t), which is 

        a part of the sheet resistance is neglected because in Cadence, we cannot control the thickness of an n-well.

        The only variables we can control are the length and width of an n-well, and varying magnitudes of L and W have an influence on the resistance.

        Given that the minimum width of an n-well is 3.6 microns, we can arbitrarily pick a value for the width. Given the resistance, sheet resistance, and 

        width, we can solve for the length.

To manually adjust the dimensions of an n-well, click on the n-well layer and use the bindkey 'Q' to edit the object. The following window should appear.

 -> length = 75 microns, width = 6 microns

The values shown above indicate the proper length and width of a 10k n-well resistor. I made sure to DRC the n-well to make sure there are no errors due to the dimensions.

If there are errors, this is due to the edges not being on the grid (each grid is 1 micron apart). Or it could also be due to the values that are not whole numbers when dividing by .15

Resulting n-well layer shown below.

Next task to do is to bring out the 'ntap' object that is used as a slot on either side of the n-well resistor in order for other resistors to connect to it. ntap is obtained using the instance bindkey 'I' under the 

"NCSU_Techlib_ami06" library. (make sure to use the layout version)       

I used 2 rows for the ntap. To adjust rows and columns of the ntap, it appears in the Instance window under "Mosaic"

As shown above, ntap is connected to either side of the n-well. Sometimes it is helpful to turn off "gravity mode" under Options -> Editer. 

At the start, the ntap does not look like how it looks above. In order to see the detail, go to Options -> Display and set Display Levels stop to 10. 

Next, the n-well needs to be defined as a resistor. The previous image of the n-well is a conductor. To do this, I chose the res_id layer, made a rectangle using bindkey 'R' 

and layed it on top of the n-well. Resulting n-well shown on the image below. 

Extracted View - used this to verify if the dimensions of the n-well results in a 10K resistance. (close enough..)

Afterwards, I DRC'ed my layout design again to check any errors. To DRC, go to Verify -> DRC and hit OK. Result will show on the log if the DRC is successful.

Prior to connecting multiple n-well resistors, the metal1 layer must be used to connect the two slots of the ntap from either side of the resistor. 

->

Next, I made a small layout of three 10K n-well resistors to resemble a portion of the DAC that we will then instantiate to make the overall 10-bit DAC. 

To make sure the schematic of three 10K n-well resistors match with it's layout, I ran LVS. 

 ->  

After running LVS, the netlists of the schematic and layout match. 

Note: Before instantiating the DAC portion and making the 10-bit DAC, I had to remove the labels ("Left" and "Bottom") so that they will be replaced by the labels that will match the labels 

on the 10-bit DAC schematic.

Additional Note: The 10K n-well resistors of this layout design will be stacked (have the same 'X' position, but vary in 'Y' position)                    

Below is the full layout of my 10-bit DAC

Top of layout zoomed in

Bottom of layout zoomed in

The circled n-well resistor as shown above is an extra 10K resistor I included in order to fulfill the 2R on the bottom of the 10-bit DAC schematic.

DRC and LVS Check

DRC:         

LVS:

Output:                             

To use LVS: Verify -> LVS -> Run

            - this will execute the LVS verification, result will show if the netlists match on the log.

            - to check output of LVS: Verify -> LVS -> Output

                      - this will compare and display the netlists of the layout and schematic design,

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